Author: ds

Status: works

The classic in digital I/O.  The 8255 appears in Comedi as a single
digital I/O subdevice with 24 channels.  The channel 0 corresponds
to the 8255's port A, bit 0; channel 23 corresponds to port C, bit
7.  Direction configuration is done in blocks, with channels 0-7,
8-15, 16-19, and 20-23 making up the 4 blocks.  The only 8255 mode
supported is mode 0.

You should enable compilation this driver if you plan to use a board
that has an 8255 chip.  For multifunction boards, the main driver will
configure the 8255 subdevice automatically.

This driver also works independently with ISA and PCI cards that
directly map the 8255 registers to I/O ports, including cards with
multiple 8255 chips.  To configure the driver for such a card, the
option list should be a list of the I/O port bases for each of the
8255 chips.  For example,

  comedi_config /dev/comedi0 8255 0x200,0x204,0x208,0x20c

Note that most PCI 8255 boards do NOT work with this driver, and
need a separate driver as a wrapper.  For those that do work, the
I/O port base address can be found in the output of 'lspci -v'.




  

Author: H Hartley Sweeten <hsweeten@visionengravers.com>

Status: untested

These boards have one or more 8255 digital I/O chips, each of which
is supported as a separate 24-channel DIO subdevice.

Boards with 24 DIO channels (1 DIO subdevice):

  PCI-7224, PCI-DIO24, PCI-DIO24H, PCI-6503, PCI-6503B, PCI-6503X,
  PXI-6503

Boards with 48 DIO channels (2 DIO subdevices):

  PCI-7248, PCI-DIO48H

Boards with 96 DIO channels (4 DIO subdevices):

  PCI-7296, PCI-DIO96H, PCI-DIO-96, PCI-DIO-96B, PXI-6508

Some of these boards also have an 8254 programmable timer/counter
chip.  This chip is not currently supported by this driver.

Interrupt support for these boards is also not currently supported.

Configuration Options: not applicable, uses PCI auto config.




  

Author: ADDI-DATA GmbH <info@addi-data.com>, H Hartley Sweeten <hsweeten@visionengravers.com>

Status: untested

Configuration options:
  None; devices are configured automatically.

This driver models the APCI-1032 as a 32-channel, digital input subdevice
plus an additional digital input subdevice to handle change-of-state (COS)
interrupts (if an interrupt handler can be set up successfully).

The COS subdevice supports comedi asynchronous read commands.

Change-Of-State (COS) interrupt configuration:

Channels 0 to 15 are interruptible. These channels can be configured
to generate interrupts based on AND/OR logic for the desired channels.

  OR logic:
  - reacts to rising or falling edges
  - interrupt is generated when any enabled channel meets the desired
    interrupt condition

  AND logic:
  - reacts to changes in level of the selected inputs
  - interrupt is generated when all enabled channels meet the desired
    interrupt condition
  - after an interrupt, a change in level must occur on the selected
    inputs to release the IRQ logic

The COS subdevice must be configured before setting up a comedi
asynchronous command:

  data[0] : INSN_CONFIG_DIGITAL_TRIG
  data[1] : trigger number (= 0)
  data[2] : configuration operation:
            - COMEDI_DIGITAL_TRIG_DISABLE = no interrupts
            - COMEDI_DIGITAL_TRIG_ENABLE_EDGES = OR (edge) interrupts
            - COMEDI_DIGITAL_TRIG_ENABLE_LEVELS = AND (level) interrupts
  data[3] : left-shift for data[4] and data[5]
  data[4] : rising-edge/high level channels
  data[5] : falling-edge/low level channels




  

Author: H Hartley Sweeten <hsweeten@visionengravers.com>

Status: untested

Configuration Options: not applicable, uses comedi PCI auto config

This board has the following features:
  - 32 optically isolated digital inputs (24V), 16 of which can
    generate change-of-state (COS) interrupts (channels 4 to 19)
  - 32 optically isolated digital outputs (10V to 36V)
  - 1 8-bit watchdog for resetting the outputs
  - 1 12-bit timer
  - 3 32-bit counters
  - 2 diagnostic inputs

The COS, timer, and counter subdevices all use the dev->read_subdev to
return the interrupt status. The sample data is updated and returned when
any of these subdevices generate an interrupt. The sample data format is:

   Bit   Description
  -----  ------------------------------------------
   31    COS interrupt
   30    timer interrupt
   29    counter 2 interrupt
   28    counter 1 interrupt
   27    counter 0 interrupt
  26:20  not used
  19:4   COS digital input state (channels 19 to 4)
   3:0   not used

The COS interrupts must be configured using an INSN_CONFIG_DIGITAL_TRIG
instruction before they can be enabled by an async command. The COS
interrupts will stay active until canceled.

The timer subdevice does not use an async command. All control is handled
by the (*insn_config).


The counter subdevice also does not use an async command. All control is
handled by the (*insn_config).





  

Author: H Hartley Sweeten <hsweeten@visionengravers.com>

Status: untested

Configuration Options: not applicable, uses comedi PCI auto config

This board has the following features:
  - 4 or 8 analog output channels
  - 2 optically isolated digital inputs
  - 2 optically isolated digital outputs
  - 1 12-bit watchdog/timer

There are 2 versions of the APCI-3501:
  - APCI-3501-4  4 analog output channels
  - APCI-3501-8  8 analog output channels

These boards use the same PCI Vendor/Device IDs. The number of output
channels used by this driver is determined by reading the EEPROM on
the board.

The watchdog/timer subdevice is not currently supported.




  

Author: nsyeow <nsyeow@pd.jaring.my>

Status: untested

Configuration Options: not applicable, uses PCI auto config

All supported devices share the same PCI device ID and are treated as a
PCI-6216 with 16 analog output channels.  On a PCI-6208, the upper 8
channels exist in registers, but don't go to DAC chips.




  

Author: H Hartley Sweeten <hsweeten@visionengravers.com>

Status: untested

One or two subdevices are setup by this driver depending on
the number of digital inputs and/or outputs provided by the
board. Each subdevice has a maximum of 32 channels.

	PCI-7230 - 2 subdevices: 0 - 16 input, 1 - 16 output
	PCI-7233 - 1 subdevice: 0 - 32 input
	PCI-7234 - 1 subdevice: 0 - 32 output
	PCI-7432 - 2 subdevices: 0 - 32 input, 1 - 32 output
	PCI-7433 - 2 subdevices: 0 - 32 input, 1 - 32 input
	PCI-7434 - 2 subdevices: 0 - 32 output, 1 - 32 output

The PCI-7230, PCI-7432 and PCI-7433 boards also support external
interrupt signals on digital input channels 0 and 1. The PCI-7233
has dual-interrupt sources for change-of-state (COS) on any 16
digital input channels of LSB and for COS on any 16 digital input
lines of MSB. Interrupts are not currently supported by this
driver.

Configuration Options: not applicable, uses comedi PCI auto config




  

Author: Michel Lachaine <mike@mikelachaine.ca>

Status: experimental

Configuration Options: not applicable, uses PCI auto config




  

Author: Emmanuel Pacaud <emmanuel.pacaud@univ-poitiers.fr>

Status: experimental

Configuration options: not applicable, uses PCI auto config


The scanned channels must be consecutive and start from 0. They must
all have the same range and aref.




  

Author: Michal Dobes <dobes@tesnet.cz>

Status: works

This driver supports AI, AO, DI and DO subdevices.
AI subdevice supports cmd and insn interface,
other subdevices support only insn interface.
For AI:
- If cmd->scan_begin_src=TRIG_EXT then trigger input is TGIN (pin 46).
- If cmd->convert_src=TRIG_EXT then trigger input is EXTTRG (pin 44).
- If cmd->start_src/stop_src=TRIG_EXT then trigger input is TGIN (pin 46).
- It is not necessary to have cmd.scan_end_arg=cmd.chanlist_len but
cmd.scan_end_arg modulo cmd.chanlist_len must by 0.
- If return value of cmdtest is 5 then you've bad channel list
(it isn't possible mixture S.E. and DIFF inputs or bipolar and unipolar
ranges).

There are some hardware limitations:
a) You cann't use mixture of unipolar/bipoar ranges or differencial/single
 ended inputs.
b) DMA transfers must have the length aligned to two samples (32 bit),
 so there is some problems if cmd->chanlist_len is odd. This driver tries
 bypass this with adding one sample to the end of the every scan and discard
 it on output but this can't be used if cmd->scan_begin_src=TRIG_FOLLOW
 and is used flag CMDF_WAKE_EOS, then driver switch to interrupt driven mode
 with interrupt after every sample.
c) If isn't used DMA then you can use only mode where
 cmd->scan_begin_src=TRIG_FOLLOW.

Configuration options:
[0] - PCI bus of device (optional)
[1] - PCI slot of device (optional)
	 If bus/slot is not specified, then first available PCI
	 card will be used.
[2] - 0= standard 8 DIFF/16 SE channels configuration
	 n = external multiplexer connected, 1 <= n <= 256
[3] - ignored
[4] - sample&hold signal - card can generate signal for external S&H board
	 0 = use SSHO(pin 45) signal is generated in onboard hardware S&H logic
	 0 != use ADCHN7(pin 23) signal is generated from driver, number say how
		long delay is requested in ns and sign polarity of the hold
		(in this case external multiplexor can serve only 128 channels)
[5] - ignored




  

Author: jeremy theler <thelerg@ib.cnea.gov.ar>

Status: works

Configuration options:
  [0] - I/O base address (set with hardware jumpers)
		address		jumper JADR
		0x300		1 (factory default)
		0x320		2
		0x340		3
		0x360		4
		0x380		5
		0x3A0		6
  [1] - Analog Input unipolar/bipolar selection
		selection	option	JUB
		bipolar		0	2-3 (factory default)
		unipolar	1	1-2
  [2] - Analog Input single-ended/differential selection
		selection	option	JCHA	JCHB
		single-ended	0	1-2	1-2 (factory default)
		differential	1	2-3	2-3

Driver for the acquisition card ADQ12-B (without any add-on).

- Analog input is subdevice 0 (16 channels single-ended or 8 differential)
- Digital input is subdevice 1 (5 channels)
- Digital output is subdevice 1 (8 channels)
- The PACER is not supported in this version




  

Author: Michal Dobes <dobes@tesnet.cz>

Status: works

Configuration options: not applicable, uses PCI auto config

This driver supports AI, AO, DI and DO subdevices.
AI subdevice supports cmd and insn interface,
other subdevices support only insn interface.

The PCI-1710 and PCI-1710HG have the same PCI device ID, so the
driver cannot distinguish between them, as would be normal for a
PCI driver.




  

Author: H Hartley Sweeten <hsweeten@visionengravers.com>

Status: untested

Configuration options: not applicable, uses PCI auto config

The PCI-1720 has 4 isolated 12-bit analog output channels with multiple
output ranges. It also has a BoardID switch to allow differentiating
multiple boards in the system.

The analog outputs can operate in two modes, immediate and synchronized.
This driver currently does not support the synchronized output mode.

Jumpers JP1 to JP4 are used to set the current sink ranges for each
analog output channel. In order to use the current sink ranges, the
unipolar 5V range must be used. The voltage output and sink output for
each channel is available on the connector as separate pins.

Jumper JP5 controls the "hot" reset state of the analog outputs.
Depending on its setting, the analog outputs will either keep the
last settings and output values or reset to the default state after
a "hot" reset. The default state for all channels is uniploar 5V range
and all the output values are 0V. To allow this feature to work, the
analog outputs are not "reset" when the driver attaches.




  

Author: yonggang <rsmgnu@gmail.com>, Ian Abbott <abbotti@mev.co.uk>

Status: works

Configuration Options: not applicable, uses comedi PCI auto config

Subdevice 0 is 8-channel AO, 16-bit, range +/- 10 V.

Subdevice 1 is 16-channel DIO.  The channels are configurable as
input or output in 2 groups (0 to 7, 8 to 15). Configuring any
channel implicitly configures all channels in the same group.





  

Author: Frank Mori Hess <fmh6jj@gmail.com>

Status: works

Configuration Options: not applicable, uses comedi PCI auto config

Subdevice 0 is the analog output.
Subdevice 1 is the offset calibration for the analog output.
Subdevice 2 is the gain calibration for the analog output.

The calibration offset and gains have quite a large effect on the
analog output, so it is possible to adjust the analog output to
have an output range significantly different from the board's
nominal output ranges. For a calibrated +/-10V range, the analog
output's offset will be set somewhere near mid-range (0x2000) and
its gain will be near maximum (0x3fff).

There is really no difference between the board's documented 0-20mA
versus 4-20mA output ranges. To pick one or the other is simply a
matter of adjusting the offset and gain calibration until the board
outputs in the desired range.




  

Author: H Hartley Sweeten <hsweeten@visionengravers.com>

Status: untested

Configuration Options: not applicable, uses PCI auto config




  

Author: Michal Dobes <dobes@tesnet.cz>

Status: untested

Configuration Options: not applicable, uses PCI auto config




  

Author: Pablo Mejia <pablo.mejia@cctechnol.com>

Status: experimental

Configuration Options:
  [0] - I/O port base address





  

Author: Zachary Ware <zach.ware@cctechnol.com>

Status: experimental

Configuration Options:
  [0] - I/O port base address
  [1] - IRQ (optional)

The board supports interrupts on change of state of the digital inputs.
The sample data returned by the async command indicates which inputs
changed state and the current state of the inputs:

	Bit 23 - IRQ Enable (1) / Disable (0)
	Bit 17 - Input 8-15 Changed State (1 = Changed, 0 = No Change)
	Bit 16 - Input 0-7 Changed State (1 = Changed, 0 = No Change)
	Bit 15 - Digital input 15
	...
	Bit 0  - Digital input 0




  

Author: Ian Abbott <abbotti@mev.co.uk>

Status: works

Configuration options:
  [0] - I/O port base address
  [1] - IRQ (optional, but commands won't work without it)

Passing a zero for an option is the same as leaving it unspecified.

SUBDEVICES

                    PC212E         PC214E         PC215E
                 -------------  -------------  -------------
  Subdevices           6              4              5
   0                 PPI-X          PPI-X          PPI-X
   1                 CTR-Y1         PPI-Y          PPI-Y
   2                 CTR-Y2         CTR-Z1*        CTR-Z1
   3                 CTR-Z1       INTERRUPT*       CTR-Z2
   4                 CTR-Z2                      INTERRUPT
   5               INTERRUPT

                    PC218E         PC272E
                 -------------  -------------
  Subdevices           7              4
   0                 CTR-X1         PPI-X
   1                 CTR-X2         PPI-Y
   2                 CTR-Y1         PPI-Z
   3                 CTR-Y2       INTERRUPT
   4                 CTR-Z1
   5                 CTR-Z2
   6               INTERRUPT

Each PPI is a 8255 chip providing 24 DIO channels.  The DIO channels
are configurable as inputs or outputs in four groups:

  Port A  - channels  0 to  7
  Port B  - channels  8 to 15
  Port CL - channels 16 to 19
  Port CH - channels 20 to 23

Only mode 0 of the 8255 chips is supported.

Each CTR is a 8254 chip providing 3 16-bit counter channels.  Each
channel is configured individually with INSN_CONFIG instructions.  The
specific type of configuration instruction is specified in data[0].
Some configuration instructions expect an additional parameter in
data[1]; others return a value in data[1].  The following configuration
instructions are supported:

  INSN_CONFIG_SET_COUNTER_MODE.  Sets the counter channel's mode and
    BCD/binary setting specified in data[1].

  INSN_CONFIG_8254_READ_STATUS.  Reads the status register value for the
    counter channel into data[1].

  INSN_CONFIG_SET_CLOCK_SRC.  Sets the counter channel's clock source as
    specified in data[1] (this is a hardware-specific value).  Not
    supported on PC214E.  For the other boards, valid clock sources are
    0 to 7 as follows:

      0.  CLK n, the counter channel's dedicated CLK input from the SK1
        connector.  (N.B. for other values, the counter channel's CLKn
        pin on the SK1 connector is an output!)
      1.  Internal 10 MHz clock.
      2.  Internal 1 MHz clock.
      3.  Internal 100 kHz clock.
      4.  Internal 10 kHz clock.
      5.  Internal 1 kHz clock.
      6.  OUT n-1, the output of counter channel n-1 (see note 1 below).
      7.  Ext Clock, the counter chip's dedicated Ext Clock input from
        the SK1 connector.  This pin is shared by all three counter
        channels on the chip.

  INSN_CONFIG_GET_CLOCK_SRC.  Returns the counter channel's current
    clock source in data[1].  For internal clock sources, data[2] is set
    to the period in ns.

  INSN_CONFIG_SET_GATE_SRC.  Sets the counter channel's gate source as
    specified in data[2] (this is a hardware-specific value).  Not
    supported on PC214E.  For the other boards, valid gate sources are 0
    to 7 as follows:

      0.  VCC (internal +5V d.c.), i.e. gate permanently enabled.
      1.  GND (internal 0V d.c.), i.e. gate permanently disabled.
      2.  GAT n, the counter channel's dedicated GAT input from the SK1
        connector.  (N.B. for other values, the counter channel's GATn
        pin on the SK1 connector is an output!)
      3.  /OUT n-2, the inverted output of counter channel n-2 (see note
        2 below).
      4.  Reserved.
      5.  Reserved.
      6.  Reserved.
      7.  Reserved.

  INSN_CONFIG_GET_GATE_SRC.  Returns the counter channel's current gate
    source in data[2].

Clock and gate interconnection notes:

  1.  Clock source OUT n-1 is the output of the preceding channel on the
  same counter subdevice if n > 0, or the output of channel 2 on the
  preceding counter subdevice (see note 3) if n = 0.

  2.  Gate source /OUT n-2 is the inverted output of channel 0 on the
  same counter subdevice if n = 2, or the inverted output of channel n+1
  on the preceding counter subdevice (see note 3) if n < 2.

  3.  The counter subdevices are connected in a ring, so the highest
  counter subdevice precedes the lowest.

The 'INTERRUPT' subdevice pretends to be a digital input subdevice.  The
digital inputs come from the interrupt status register.  The number of
channels matches the number of interrupt sources.  The PC214E does not
have an interrupt status register; see notes on 'INTERRUPT SOURCES'
below.

INTERRUPT SOURCES

                    PC212E         PC214E         PC215E
                 -------------  -------------  -------------
  Sources              6              1              6
   0               PPI-X-C0       JUMPER-J5      PPI-X-C0
   1               PPI-X-C3                      PPI-X-C3
   2              CTR-Y1-OUT1                    PPI-Y-C0
   3              CTR-Y2-OUT1                    PPI-Y-C3
   4              CTR-Z1-OUT1                   CTR-Z1-OUT1
   5              CTR-Z2-OUT1                   CTR-Z2-OUT1

                    PC218E         PC272E
                 -------------  -------------
  Sources              6              6
   0              CTR-X1-OUT1     PPI-X-C0
   1              CTR-X2-OUT1     PPI-X-C3
   2              CTR-Y1-OUT1     PPI-Y-C0
   3              CTR-Y2-OUT1     PPI-Y-C3
   4              CTR-Z1-OUT1     PPI-Z-C0
   5              CTR-Z2-OUT1     PPI-Z-C3

When an interrupt source is enabled in the interrupt source enable
register, a rising edge on the source signal latches the corresponding
bit to 1 in the interrupt status register.

When the interrupt status register value as a whole (actually, just the
6 least significant bits) goes from zero to non-zero, the board will
generate an interrupt.  No further interrupts will occur until the
interrupt status register is cleared to zero.  To clear a bit to zero in
the interrupt status register, the corresponding interrupt source must
be disabled in the interrupt source enable register (there is no
separate interrupt clear register).

The PC214E does not have an interrupt source enable register or an
interrupt status register; its 'INTERRUPT' subdevice has a single
channel and its interrupt source is selected by the position of jumper
J5.

COMMANDS

The driver supports a read streaming acquisition command on the
'INTERRUPT' subdevice.  The channel list selects the interrupt sources
to be enabled.  All channels will be sampled together (convert_src ==
TRIG_NOW).  The scan begins a short time after the hardware interrupt
occurs, subject to interrupt latencies (scan_begin_src == TRIG_EXT,
scan_begin_arg == 0).  The value read from the interrupt status register
is packed into a short value, one bit per requested channel, in the
order they appear in the channel list.




  

Author: Ian Abbott <abbotti@mev.co.uk>

Status: works

Configuration options:
  none

Manual configuration of PCI(e) cards is not supported; they are configured
automatically.

SUBDEVICES

                    PCI215         PCIe215        PCIe236
                 -------------  -------------  -------------
  Subdevices           5              8              8
   0                 PPI-X          PPI-X          PPI-X
   1                 PPI-Y          UNUSED         UNUSED
   2                 CTR-Z1         PPI-Y          UNUSED
   3                 CTR-Z2         UNUSED         UNUSED
   4               INTERRUPT        CTR-Z1         CTR-Z1
   5                                CTR-Z2         CTR-Z2
   6                                TIMER          TIMER
   7                              INTERRUPT      INTERRUPT


                    PCI272         PCIe296
                 -------------  -------------
  Subdevices           4              8
   0                 PPI-X          PPI-X1
   1                 PPI-Y          PPI-X2
   2                 PPI-Z          PPI-Y1
   3               INTERRUPT        PPI-Y2
   4                                CTR-Z1
   5                                CTR-Z2
   6                                TIMER
   7                              INTERRUPT

Each PPI is a 8255 chip providing 24 DIO channels.  The DIO channels
are configurable as inputs or outputs in four groups:

  Port A  - channels  0 to  7
  Port B  - channels  8 to 15
  Port CL - channels 16 to 19
  Port CH - channels 20 to 23

Only mode 0 of the 8255 chips is supported.

Each CTR is a 8254 chip providing 3 16-bit counter channels.  Each
channel is configured individually with INSN_CONFIG instructions.  The
specific type of configuration instruction is specified in data[0].
Some configuration instructions expect an additional parameter in
data[1]; others return a value in data[1].  The following configuration
instructions are supported:

  INSN_CONFIG_SET_COUNTER_MODE.  Sets the counter channel's mode and
    BCD/binary setting specified in data[1].

  INSN_CONFIG_8254_READ_STATUS.  Reads the status register value for the
    counter channel into data[1].

  INSN_CONFIG_SET_CLOCK_SRC.  Sets the counter channel's clock source as
    specified in data[1] (this is a hardware-specific value).  Not
    supported on PC214E.  For the other boards, valid clock sources are
    0 to 7 as follows:

      0.  CLK n, the counter channel's dedicated CLK input from the SK1
        connector.  (N.B. for other values, the counter channel's CLKn
        pin on the SK1 connector is an output!)
      1.  Internal 10 MHz clock.
      2.  Internal 1 MHz clock.
      3.  Internal 100 kHz clock.
      4.  Internal 10 kHz clock.
      5.  Internal 1 kHz clock.
      6.  OUT n-1, the output of counter channel n-1 (see note 1 below).
      7.  Ext Clock, the counter chip's dedicated Ext Clock input from
        the SK1 connector.  This pin is shared by all three counter
        channels on the chip.

    For the PCIe boards, clock sources in the range 0 to 31 are allowed
    and the following additional clock sources are defined:

      8.  HIGH logic level.
      9.  LOW logic level.
     10.  "Pattern present" signal.
     11.  Internal 20 MHz clock.

  INSN_CONFIG_GET_CLOCK_SRC.  Returns the counter channel's current
    clock source in data[1].  For internal clock sources, data[2] is set
    to the period in ns.

  INSN_CONFIG_SET_GATE_SRC.  Sets the counter channel's gate source as
    specified in data[2] (this is a hardware-specific value).  Not
    supported on PC214E.  For the other boards, valid gate sources are 0
    to 7 as follows:

      0.  VCC (internal +5V d.c.), i.e. gate permanently enabled.
      1.  GND (internal 0V d.c.), i.e. gate permanently disabled.
      2.  GAT n, the counter channel's dedicated GAT input from the SK1
        connector.  (N.B. for other values, the counter channel's GATn
        pin on the SK1 connector is an output!)
      3.  /OUT n-2, the inverted output of counter channel n-2 (see note
        2 below).
      4.  Reserved.
      5.  Reserved.
      6.  Reserved.
      7.  Reserved.

    For the PCIe boards, gate sources in the range 0 to 31 are allowed;
    the following additional clock sources and clock sources 6 and 7 are
    (re)defined:

      6.  /GAT n, negated version of the counter channel's dedicated
        GAT input (negated version of gate source 2).
      7.  OUT n-2, the non-inverted output of counter channel n-2
        (negated version of gate source 3).
      8.  "Pattern present" signal, HIGH while pattern present.
      9.  "Pattern occurred" latched signal, latches HIGH when pattern
        occurs.
     10.  "Pattern gone away" latched signal, latches LOW when pattern
        goes away after it occurred.
     11.  Negated "pattern present" signal, LOW while pattern present
        (negated version of gate source 8).
     12.  Negated "pattern occurred" latched signal, latches LOW when
        pattern occurs (negated version of gate source 9).
     13.  Negated "pattern gone away" latched signal, latches LOW when
        pattern goes away after it occurred (negated version of gate
        source 10).

  INSN_CONFIG_GET_GATE_SRC.  Returns the counter channel's current gate
    source in data[2].

Clock and gate interconnection notes:

  1.  Clock source OUT n-1 is the output of the preceding channel on the
  same counter subdevice if n > 0, or the output of channel 2 on the
  preceding counter subdevice (see note 3) if n = 0.

  2.  Gate source /OUT n-2 is the inverted output of channel 0 on the
  same counter subdevice if n = 2, or the inverted output of channel n+1
  on the preceding counter subdevice (see note 3) if n < 2.

  3.  The counter subdevices are connected in a ring, so the highest
  counter subdevice precedes the lowest.

The 'TIMER' subdevice is a free-running 32-bit timer subdevice.

The 'INTERRUPT' subdevice pretends to be a digital input subdevice.  The
digital inputs come from the interrupt status register.  The number of
channels matches the number of interrupt sources.  The PC214E does not
have an interrupt status register; see notes on 'INTERRUPT SOURCES'
below.

INTERRUPT SOURCES

                    PCI215         PCIe215        PCIe236
                 -------------  -------------  -------------
  Sources              6              6              6
   0               PPI-X-C0       PPI-X-C0       PPI-X-C0
   1               PPI-X-C3       PPI-X-C3       PPI-X-C3
   2               PPI-Y-C0       PPI-Y-C0        unused
   3               PPI-Y-C3       PPI-Y-C3        unused
   4              CTR-Z1-OUT1    CTR-Z1-OUT1    CTR-Z1-OUT1
   5              CTR-Z2-OUT1    CTR-Z2-OUT1    CTR-Z2-OUT1

                    PCI272         PCIe296
                 -------------  -------------
  Sources              6              6
   0               PPI-X-C0       PPI-X1-C0
   1               PPI-X-C3       PPI-X1-C3
   2               PPI-Y-C0       PPI-Y1-C0
   3               PPI-Y-C3       PPI-Y1-C3
   4               PPI-Z-C0      CTR-Z1-OUT1
   5               PPI-Z-C3      CTR-Z2-OUT1

When an interrupt source is enabled in the interrupt source enable
register, a rising edge on the source signal latches the corresponding
bit to 1 in the interrupt status register.

When the interrupt status register value as a whole (actually, just the
6 least significant bits) goes from zero to non-zero, the board will
generate an interrupt.  The interrupt will remain asserted until the
interrupt status register is cleared to zero.  To clear a bit to zero in
the interrupt status register, the corresponding interrupt source must
be disabled in the interrupt source enable register (there is no
separate interrupt clear register).

COMMANDS

The driver supports a read streaming acquisition command on the
'INTERRUPT' subdevice.  The channel list selects the interrupt sources
to be enabled.  All channels will be sampled together (convert_src ==
TRIG_NOW).  The scan begins a short time after the hardware interrupt
occurs, subject to interrupt latencies (scan_begin_src == TRIG_EXT,
scan_begin_arg == 0).  The value read from the interrupt status register
is packed into a short value, one bit per requested channel, in the
order they appear in the channel list.




  

Author: Ian Abbott <abbotti@mev.co.uk>

Status: works

Configuration options - PC36AT:
  [0] - I/O port base address
  [1] - IRQ (optional)

The PC36AT board has a single 8255 appearing as subdevice 0.

Subdevice 1 pretends to be a digital input device, but it always returns
0 when read. However, if you run a command with scan_begin_src=TRIG_EXT,
a rising edge on port C bit 3 acts as an external trigger, which can be
used to wake up tasks.  This is like the comedi_parport device, but the
only way to physically disable the interrupt on the PC36AT is to remove
the IRQ jumper.  If no interrupt is connected, then subdevice 1 is
unused.




  

Author: Ian Abbott <abbotti@mev.co.uk>

Status: works

Configuration options:
  [0] - I/O port base address

The board appears as one subdevice, with 16 digital outputs, each
connected to a reed-relay. Relay contacts are closed when output is 1.
The state of the outputs can be read.




  

Author: Ian Abbott <abbotti@mev.co.uk>

Status: works, but see caveats

  - ao_insn read/write
  - ao_do_cmd mode with the following sources:

    - start_src         TRIG_INT        TRIG_EXT
    - scan_begin_src    TRIG_TIMER      TRIG_EXT
    - convert_src       TRIG_NOW
    - scan_end_src      TRIG_COUNT
    - stop_src          TRIG_COUNT      TRIG_EXT        TRIG_NONE

    The channel list must contain at least one channel with no repeated
    channels.  The scan end count must equal the number of channels in
    the channel list.

    There is only one external trigger source so only one of start_src,
    scan_begin_src or stop_src may use TRIG_EXT.

Configuration options:
  none

Manual configuration of PCI cards is not supported; they are configured
automatically.

Output range selection - PCI224:

  Output ranges on PCI224 are partly software-selectable and partly
  hardware-selectable according to jumper LK1.  All channels are set
  to the same range:

  - LK1 position 1-2 (factory default) corresponds to the following
    comedi ranges:

      0: [-10V,+10V]; 1: [-5V,+5V]; 2: [-2.5V,+2.5V], 3: [-1.25V,+1.25V],
      4: [0,+10V],    5: [0,+5V],   6: [0,+2.5V],     7: [0,+1.25V]

  - LK1 position 2-3 corresponds to the following Comedi ranges, using
    an external voltage reference:

      0: [-Vext,+Vext],
      1: [0,+Vext]

Output range selection - PCI234:

  Output ranges on PCI234 are hardware-selectable according to jumper
  LK1 which affects all channels, and jumpers LK2, LK3, LK4 and LK5
  which affect channels 0, 1, 2 and 3 individually.  LK1 chooses between
  an internal 5V reference and an external voltage reference (Vext).
  LK2/3/4/5 choose (per channel) to double the reference or not according
  to the following table:

    LK1 position   LK2/3/4/5 pos  Comedi range
    -------------  -------------  --------------
    2-3 (factory)  1-2 (factory)  0: [-10V,+10V]
    2-3 (factory)  2-3            1: [-5V,+5V]
    1-2            1-2 (factory)  2: [-2*Vext,+2*Vext]
    1-2            2-3            3: [-Vext,+Vext]


  1) All channels on the PCI224 share the same range.  Any change to the
     range as a result of insn_write or a streaming command will affect
     the output voltages of all channels, including those not specified
     by the instruction or command.

  2) For the analog output command,  the first scan may be triggered
     falsely at the start of acquisition.  This occurs when the DAC scan
     trigger source is switched from 'none' to 'timer' (scan_begin_src =
     TRIG_TIMER) or 'external' (scan_begin_src == TRIG_EXT) at the start
     of acquisition and the trigger source is at logic level 1 at the
     time of the switch.  This is very likely for TRIG_TIMER.  For
     TRIG_EXT, it depends on the state of the external line and whether
     the CR_INVERT flag has been set.  The remaining scans are triggered
     correctly.




  

Author: Allan Willcox <allanwillcox@ozemail.com.au>, Steve D Sharples <steve.sharples@nottingham.ac.uk>, Ian Abbott <abbotti@mev.co.uk>

Status: works

Configuration options:
  none

Manual configuration of PCI cards is not supported; they are configured
automatically.

The PCI230+ and PCI260+ have the same PCI device IDs as the PCI230 and
PCI260, but can be distinguished by the size of the PCI regions.  A
card will be configured as a "+" model if detected as such.


                PCI230(+)    PCI260(+)
                ---------    ---------
  Subdevices       3            1
        0          AI           AI
        1          AO
        2          DIO

AI Subdevice:

  The AI subdevice has 16 single-ended channels or 8 differential
  channels.

  The PCI230 and PCI260 cards have 12-bit resolution.  The PCI230+ and
  PCI260+ cards have 16-bit resolution.

  For differential mode, use inputs 2N and 2N+1 for channel N (e.g. use
  inputs 14 and 15 for channel 7).  If the card is physically a PCI230
  or PCI260 then it actually uses a "pseudo-differential" mode where the
  inputs are sampled a few microseconds apart.  The PCI230+ and PCI260+
  use true differential sampling.  Another difference is that if the
  card is physically a PCI230 or PCI260, the inverting input is 2N,
  whereas for a PCI230+ or PCI260+ the inverting input is 2N+1.  So if a
  PCI230 is physically replaced by a PCI230+ (or a PCI260 with a
  PCI260+) and differential mode is used, the differential inputs need
  to be physically swapped on the connector.

  The following input ranges are supported:

    0 => [-10, +10] V
    1 => [-5, +5] V
    2 => [-2.5, +2.5] V
    3 => [-1.25, +1.25] V
    4 => [0, 10] V
    5 => [0, 5] V
    6 => [0, 2.5] V

AI Commands:

  +=========+==============+===========+============+==========+
  |start_src|scan_begin_src|convert_src|scan_end_src| stop_src |
  +=========+==============+===========+============+==========+
  |TRIG_NOW | TRIG_FOLLOW  |TRIG_TIMER | TRIG_COUNT |TRIG_NONE |
  |TRIG_INT |              |TRIG_EXT(3)|            |TRIG_COUNT|
  |         |              |TRIG_INT   |            |          |
  |         |--------------|-----------|            |          |
  |         | TRIG_TIMER(1)|TRIG_TIMER |            |          |
  |         | TRIG_EXT(2)  |           |            |          |
  |         | TRIG_INT     |           |            |          |
  +---------+--------------+-----------+------------+----------+

  Note 1: If AI command and AO command are used simultaneously, only
          one may have scan_begin_src == TRIG_TIMER.

  Note 2: For PCI230 and PCI230+, scan_begin_src == TRIG_EXT uses
          DIO channel 16 (pin 49) which will need to be configured as
          a digital input.  For PCI260+, the EXTTRIG/EXTCONVCLK input
          (pin 17) is used instead.  For PCI230, scan_begin_src ==
          TRIG_EXT is not supported.  The trigger is a rising edge
          on the input.

  Note 3: For convert_src == TRIG_EXT, the EXTTRIG/EXTCONVCLK input
          (pin 25 on PCI230(+), pin 17 on PCI260(+)) is used.  The
          convert_arg value is interpreted as follows:

            convert_arg == (CR_EDGE | 0) => rising edge
            convert_arg == (CR_EDGE | CR_INVERT | 0) => falling edge
            convert_arg == 0 => falling edge (backwards compatibility)
            convert_arg == 1 => rising edge (backwards compatibility)

  All entries in the channel list must use the same analogue reference.
  If the analogue reference is not AREF_DIFF (not differential) each
  pair of channel numbers (0 and 1, 2 and 3, etc.) must use the same
  input range.  The input ranges used in the sequence must be all
  bipolar (ranges 0 to 3) or all unipolar (ranges 4 to 6).  The channel
  sequence must consist of 1 or more identical subsequences.  Within the
  subsequence, channels must be in ascending order with no repeated
  channels.  For example, the following sequences are valid: 0 1 2 3
  (single valid subsequence), 0 2 3 5 0 2 3 5 (repeated valid
  subsequence), 1 1 1 1 (repeated valid subsequence).  The following
  sequences are invalid: 0 3 2 1 (invalid subsequence), 0 2 3 5 0 2 3
  (incompletely repeated subsequence).  Some versions of the PCI230+ and
  PCI260+ have a bug that requires a subsequence longer than one entry
  long to include channel 0.

AO Subdevice:

  The AO subdevice has 2 channels with 12-bit resolution.
  The following output ranges are supported:
    0 => [0, 10] V
    1 => [-10, +10] V

AO Commands:

  +=========+==============+===========+============+==========+
  |start_src|scan_begin_src|convert_src|scan_end_src| stop_src |
  +=========+==============+===========+============+==========+
  |TRIG_INT | TRIG_TIMER(1)| TRIG_NOW  | TRIG_COUNT |TRIG_NONE |
  |         | TRIG_EXT(2)  |           |            |TRIG_COUNT|
  |         | TRIG_INT     |           |            |          |
  +---------+--------------+-----------+------------+----------+

  Note 1: If AI command and AO command are used simultaneously, only
          one may have scan_begin_src == TRIG_TIMER.

  Note 2: scan_begin_src == TRIG_EXT is only supported if the card is
          configured as a PCI230+ and is only supported on later
          versions of the card.  As a card configured as a PCI230+ is
          not guaranteed to support external triggering, please consider
          this support to be a bonus.  It uses the EXTTRIG/ EXTCONVCLK
          input (PCI230+ pin 25).  Triggering will be on the rising edge
          unless the CR_INVERT flag is set in scan_begin_arg.

  The channels in the channel sequence must be in ascending order with
  no repeats.  All entries in the channel sequence must use the same
  output range.

DIO Subdevice:

  The DIO subdevice is a 8255 chip providing 24 DIO channels.  The DIO
  channels are configurable as inputs or outputs in four groups:

    Port A  - channels  0 to  7
    Port B  - channels  8 to 15
    Port CL - channels 16 to 19
    Port CH - channels 20 to 23

  Only mode 0 of the 8255 chip is supported.

  Bit 0 of port C (DIO channel 16) is also used as an external scan
  trigger input for AI commands on PCI230 and PCI230+, so would need to
  be configured as an input to use it for that purpose.




  

Author: Ian Abbott <abbotti@mev.co.uk>

Status: works

Configuration options:
  none

Manual configuration of PCI board (PCI236) is not supported; it is
configured automatically.

The PCI236 board has a single 8255 appearing as subdevice 0.

Subdevice 1 pretends to be a digital input device, but it always
returns 0 when read. However, if you run a command with
scan_begin_src=TRIG_EXT, a rising edge on port C bit 3 acts as an
external trigger, which can be used to wake up tasks.  This is like
the comedi_parport device.  If no interrupt is connected, then
subdevice 1 is unused.




  

Author: Ian Abbott <abbotti@mev.co.uk>

Status: works

Configuration options: not applicable, uses PCI auto config

The board appears as one subdevice, with 16 digital outputs, each
connected to a reed-relay. Relay contacts are closed when output is 1.
The state of the outputs can be read.




  

Author: Dan Block

Status: unknown

Configuration Options:
	[0] - base address




  

Author: ds

Status: experimental

Author: Ivan Martinez <imr@oersted.dtu.dk>, Frank Mori Hess <fmhess@users.sourceforge.net>

Status: There are many reports of the driver being used with most of the supported cards. Despite no detailed log is maintained, it can be said that the driver is quite tested and stable.

The boards may be autocalibrated using the comedi_calibrate
utility.

Configuration options: not applicable, uses PCI auto config

For commands, the scanned channels must be consecutive
(i.e. 4-5-6-7, 2-3-4,...), and must all have the same
range and aref.

AI Triggering:
For start_src == TRIG_EXT, the A/D EXTERNAL TRIGGER IN (pin 45) is used.
For 1602 series, the start_arg is interpreted as follows:
	start_arg == 0                   => gated trigger (level high)
	start_arg == CR_INVERT           => gated trigger (level low)
	start_arg == CR_EDGE             => Rising edge
	start_arg == CR_EDGE | CR_INVERT => Falling edge
For the other boards the trigger will be done on rising edge




  

Author: Frank Mori Hess <fmhess@users.sourceforge.net>

Status: works

Configuration options:
  None.

Manual attachment of PCI cards with the comedi_config utility is not
supported by this driver; they are attached automatically.

These boards may be autocalibrated with the comedi_calibrate utility.

To select the bnc trigger input on the 4020 (instead of the dio input),
specify a nonzero channel in the chanspec.  If you wish to use an external
master clock on the 4020, you may do so by setting the scan_begin_src
to TRIG_OTHER, and using an INSN_CONFIG_TIMER_1 configuration insn
to configure the divisor to use for the external clock.

Some devices are not identified because the PCI device IDs are not yet
known. If you have such a board, please let the maintainers know.




  

Author: Ivan Martinez <ivanmr@altavista.com> Frank Mori Hess <fmhess@users.sourceforge.net>

Status: works

Configuration options: not applicable, uses PCI auto config

Only simple analog output writing is supported.




  

Author: Richard Bytheway

Status: experimental

Written to support the PCIM-DAS1602/16 and PCIe-DAS1602/16.

Configuration Options:
  none

Manual configuration of PCI(e) cards is not supported; they are configured
automatically.

Developed from cb_pcidas and skel by Richard Bytheway (mocelet@sucs.org).
Only supports DIO, AO and simple AI in it's present form.
No interrupts, multi channel or FIFO AI,
although the card looks like it could support this.





  

Author: Calin Culianu <calin@ajvar.org>

Status: works

All features of the PCIM-DDA06-16 board are supported.
This board has 6 16-bit AO channels, and the usual 8255 DIO setup.
(24 channels, configurable in banks of 8 and 4, etc.).
This board does not support commands.

The board has a peculiar way of specifying AO gain/range settings -- You have
1 jumper bank on the card, which either makes all 6 AO channels either
5 Volt unipolar, 5V bipolar, 10 Volt unipolar or 10V bipolar.

Since there is absolutely _no_ way to tell in software how this jumper is set
(well, at least according to the rather thin spec. from Measurement Computing
that comes with the board), the driver assumes the jumper is at its factory
default setting of +/-5V.

Also of note is the fact that this board features another jumper, whose
state is also completely invisible to software.  It toggles two possible AO
output modes on the board:

  - Update Mode: Writing to an AO channel instantaneously updates the actual
    signal output by the DAC on the board (this is the factory default).
  - Simultaneous XFER Mode: Writing to an AO channel has no effect until
    you read from any one of the AO channels.  This is useful for loading
    all 6 AO values, and then reading from any one of the AO channels on the
    device to instantly update all 6 AO values in unison.  Useful for some
    control apps, I would assume? If your jumper is in this setting, then you
    need to issue your comedi_data_write()s to load all the values you want,
    then issue one comedi_data_read() on any channel on the AO subdevice
    to initiate the simultaneous XFER.

Configuration Options: not applicable, uses PCI auto config




  

Author: ds

Status: works

This driver allows you to 'bond' (merge) multiple comedi subdevices
(coming from possibly difference boards and/or drivers) together.  For
example, if you had a board with 2 different DIO subdevices, and
another with 1 DIO subdevice, you could 'bond' them with this driver
so that they look like one big fat DIO subdevice.  This makes writing
applications slightly easier as you don't have to worry about managing
different subdevices in the application -- you just worry about
indexing one linear array of channel id's.

Right now only DIO subdevices are supported as that's the personal itch
I am scratching with this driver.  If you want to add support for AI and AO
subdevs, go right on ahead and do so!

Commands aren't supported -- although it would be cool if they were.

Configuration Options:
  List of comedi-minors to bond.  All subdevices of the same type
  within each minor will be concatenated together in the order given here.




  

Author: ds

Status: works in immediate mode

A cheap and easy way to get a few more digital I/O lines. Steal
additional parallel ports from old computers or your neighbors'
computers.

Option list:
  0: I/O port base for the parallel port.
  1: IRQ (optional)

Parallel Port Lines:

	 pin   subdev  chan  type  name
	-----  ------  ----  ----  --------------
	  1      2       0    DO   strobe
	  2      0       0    DIO  data 0
	  3      0       1    DIO  data 1
	  4      0       2    DIO  data 2
	  5      0       3    DIO  data 3
	  6      0       4    DIO  data 4
	  7      0       5    DIO  data 5
	  8      0       6    DIO  data 6
	  9      0       7    DIO  data 7
	 10      1       3    DI   ack
	 11      1       4    DI   busy
	 12      1       2    DI   paper out
	 13      1       1    DI   select in
	 14      2       1    DO   auto LF
	 15      1       0    DI   error
	 16      2       2    DO   init
	 17      2       3    DO   select printer
	18-25                      ground

When an IRQ is configured subdevice 3 pretends to be a digital
input subdevice, but it always returns 0 when read. However, if
you run a command with scan_begin_src=TRIG_EXT, it uses pin 10
as a external trigger, which can be used to wake up tasks.




  

Author: Joachim Wuttke <Joachim.Wuttke@icn.siemens.de>, Frank Mori Hess <fmhess@users.sourceforge.net>, ds

Status: works

This driver is mainly for testing purposes, but can also be used to
generate sample waveforms on systems that don't have data acquisition
hardware.

Auto-configuration is the default mode if no parameter is supplied during
module loading. Manual configuration requires COMEDI userspace tool.
To disable auto-configuration mode, pass "noauto=1" parameter for module
loading. Refer modinfo or MODULE_PARM_DESC description below for details.

Auto-configuration options:
  Refer modinfo or MODULE_PARM_DESC description below for details.

Manual configuration options:
  [0] - Amplitude in microvolts for fake waveforms (default 1 volt)
  [1] - Period in microseconds for fake waveforms (default 0.1 sec)

Generates a sawtooth wave on channel 0, square wave on channel 1, additional
waveforms could be added to other channels (currently they return flatline
zero volts).




  

Author: Stefano Rivoir <s.rivoir@gts.it>

Status: works

Configuration Options: not applicable, uses comedi PCI auto config




  

Author: H Hartley Sweeten <hsweeten@visionengravers.com>

Status: unknown

Configuration options:
	[0] - I/O port base




  

Author: Anders Blomdell <anders.blomdell@control.lth.se>

Status: works

Much of the functionality of this driver was determined from reading
the source code for the Windows driver.

The FPGA on the board requires firmware, which is available from

Configuration options: not applicable, uses PCI auto config




  

Author: Warren Jasper, ds, Frank Hess

Status: works

This is the PCMCIA-specific support split off from the
das08 driver.

Configuration Options: none, uses PCMCIA auto config

Command support does not exist, but could be added for this board.




  

Author: Warren Jasper, ds, Frank Hess

Status: works

This is the ISA/PC-104-specific support split off from the das08 driver.

Configuration Options:
	[0] - base io address




  

Author: Warren Jasper, ds, Frank Hess

Status: works

This is the PCI-specific support split off from the das08 driver.

Configuration Options: not applicable, uses PCI auto config




  

Author: Sam Moore, Warren Jasper, ds, Chris Baugher, Frank Hess, Roman Fietze

Status: works

A rewrite of the das16 and das1600 drivers.


Passing a zero for an option is the same as leaving it unspecified.




  

Author: Frank Mori Hess <fmhess@users.sourceforge.net>

Status: works

This driver supports a single board - the CIO-DAS16/M1. As far as I know,
there are no other boards that have the same register layout. Even the
CIO-DAS16/M1/16 is significantly different.

I was _barely_ able to reach the full 1 MHz capability of this board, using
a hard real-time interrupt (set the TRIG_RT flag in your struct comedi_cmd
and use rtlinux or RTAI). The board can't do dma, so the bottleneck is
pulling the data across the ISA bus. I timed the interrupt handler, and it
took my computer ~470 microseconds to pull 512 samples from the board. So
at 1 Mhz sampling rate, expect your CPU to be spending almost all of its
time in the interrupt handler.

This board has some unusual restrictions for its channel/gain list.  If the
list has 2 or more channels in it, then two conditions must be satisfied:
(1) - even/odd channels must appear at even/odd indices in the list
(2) - the list must have an even number of entries.

Configuration options:
  [0] - base io address
  [1] - irq (optional, but you probably want it)

irq can be omitted, although the cmd interface will not work without it.




  

Author: Frank Mori Hess <fmhess@users.sourceforge.net>

Status: works

Configuration options:
  [0] - I/O port base address
  [1] - IRQ (optional, required for analog input cmd support)
  [2] - DMA0 (optional, requires irq)
  [3] - DMA1 (optional, requires irq and dma0)

analog input cmd triggers supported:

  start_src		TRIG_NOW	command starts immediately
			TRIG_EXT	command starts on external pin TGIN

  scan_begin_src	TRIG_FOLLOW	paced/external scans start immediately
			TRIG_TIMER	burst scans start periodically
			TRIG_EXT	burst scans start on external pin XPCLK

  scan_end_src	TRIG_COUNT	scan ends after last channel

  convert_src	TRIG_TIMER	paced/burst conversions are timed
			TRIG_EXT	conversions on external pin XPCLK
					(requires scan_begin_src == TRIG_FOLLOW)

  stop_src		TRIG_COUNT	command stops after stop_arg scans
			TRIG_EXT	command stops on external pin TGIN
			TRIG_NONE	command runs until canceled

If TRIG_EXT is used for both the start_src and stop_src, the first TGIN
trigger starts the command, and the second trigger will stop it. If only
one is TRIG_EXT, the first trigger will either stop or start the command.
The external pin TGIN is normally set for negative edge triggering. It
can be set to positive edge with the CR_INVERT flag. If TRIG_EXT is used
for both the start_src and stop_src they must have the same polarity.

Minimum conversion speed is limited to 64 microseconds (convert_arg <= 64000)
for 'burst' scans. This limitation does not apply for 'paced' scans. The
maximum conversion speed is limited by the board (convert_arg >= ai_speed).
Maximum conversion speeds are not always achievable depending on the
board setup (see user manual).


The waveform analog output on the 'ao' cards is not supported.
If you need it, send me (Frank Hess) an email.




  

Author: H Hartley Sweeten <hsweeten@visionengravers.com>

Status: unknown

Configuration Options:
  [0] - I/O base address
  [1] - IRQ (optional, needed for async command support)




  

Author: Frank Mori Hess <fmhess@users.sourceforge.net>

Status: works, cio-das802/16 untested - email me if you have tested it

Configuration options:
[0] - I/O port base address
[1] - IRQ (optional, required for timed or externally triggered conversions)


	All entries in the channel/gain list must use the same gain and be
	consecutive channels counting upwards in channel number (these are
	hardware limitations.)

	I've never tested the gain setting stuff since I only have a
	DAS-800 board with fixed gain.

	The cio-das802/16 does not have a fifo-empty status bit!  Therefore
	only fifo-half-full transfers are possible with this card.

cmd triggers supported:
	start_src:      TRIG_NOW | TRIG_EXT
	scan_begin_src: TRIG_FOLLOW
	scan_end_src:   TRIG_COUNT
	convert_src:    TRIG_TIMER | TRIG_EXT
	stop_src:       TRIG_NONE | TRIG_COUNT




  

Author: Perry J. Piplani <perry.j.piplani@nasa.gov>

Status: experimental

Configuration Options:
	comedi_config /dev/comedi0 dmm32at baseaddr,irq

This driver is for the Diamond Systems MM-32-AT board
	http://www.diamondsystems.com/products/diamondmm32at

It is being used on several projects inside NASA, without
problems so far. For analog input commands, TRIG_EXT is not
yet supported.




  

Author: ds

Status: works

This driver can autoprobe the type of board.

Configuration options:
[0] - I/O port base address
[1] - unused
[2] - A/D reference 0=differential, 1=single-ended
[3] - A/D range
	  0 = [-10, 10]
	  1 = [0,10]
[4] - D/A 0 range
	  0 = [-10, 10]
	  1 = [-5,5]
	  2 = [-2.5,2.5]
	  3 = [0,10]
	  4 = [0,5]
[5] - D/A 1 range (same choices)




  

Author: ds

Status: works

Configuration options:
  [0] - I/O port base address
  [1] - IRQ (optional, needed for async command support)
  [2] - A/D reference (# of analog inputs)
	   0 = single-ended (16 channels)
	   1 = differential (8 channels)
	   2 = pseudo-differential (16 channels)
  [3] - A/D range (deprecated, see below)
  [4] - D/A 0 range (deprecated, see below)
  [5] - D/A 1 range (deprecated, see below)





  

Author: ds

Status: complete

Configuration options:
[0] - I/O port base address
[1] - IRQ

This card has 16 analog inputs multiplexed onto a 12 bit ADC.  There
is a minimally useful onboard clock.  The base frequency for the
clock is selected by jumpers, and the clock divider can be selected
via programmed I/O.  Unfortunately, the clock divider can only be
a power of 10, from 1 to 10^7, of which only 3 or 4 are useful.  In
addition, the clock does not seem to be very accurate.




  

Author: ds

Status: mostly complete, untested

I'm not sure anyone has ever tested this board.  If you have information
contrary, please update.

Configuration options:
[0] - I/O port base base address
[1] - IRQ (unused)
[2] - Voltage unipolar/bipolar configuration
	0 == unipolar 5V  (0V -- +5V)
	1 == bipolar 5V  (-5V -- +5V)
[3] - Current offset configuration
	0 == disabled  (0mA -- +32mAV)
	1 == enabled  (+4mA -- +20mAV)
[4] - Firmware program configuration
	0 == program 1 (see manual table 5-4)
	1 == program 2 (see manual table 5-4)
	2 == program 3 (see manual table 5-4)
	3 == program 4 (see manual table 5-4)
[5] - Analog output 0 range configuration
	0 == voltage
	1 == current
[6] - Analog output 1 range configuration (same options)
[7] - Analog output 2 range configuration (same options)
[8] - Analog output 3 range configuration (same options)
[9] - Analog output 4 range configuration (same options)
[10] - Analog output 5 range configuration (same options)
[11] - Analog output 6 range configuration (same options)
[12] - Analog output 7 range configuration (same options)




  

Author: ds

Status: complete

A very simple digital I/O card.  Four banks of 8 lines, each bank
is configurable for input or output.  One wonders why it takes a
50 page manual to describe this thing.

The driver (which, btw, is much less than 50 pages) has 1 subdevice
with 32 channels, configurable in groups of 8.

Configuration options:
[0] - I/O port base base address




  

Author: ds

Status: complete

Configuration options:
  [0] - I/O port base address
  [1] - IRQ (optional, required for async command support)
  [2] - DMA 1 (optional, required for async command support)
  [3] - DMA 2 (optional, required for async command support)
  [4] - AI jumpered for 0=single ended, 1=differential
  [5] - AI jumpered for 0=straight binary, 1=2's complement
  [6] - AO 0 data format (deprecated, see below)
  [7] - AO 1 data format (deprecated, see below)
  [8] - AI jumpered for 0=[-10,10]V, 1=[0,10], 2=[-5,5], 3=[0,5]
  [9] - AO channel 0 range (deprecated, see below)
  [10]- AO channel 1 range (deprecated, see below)





  

Author: ds

Status: works

Configuration Options: not applicable, uses PCI auto config

There is code to support AI commands, but it may not work.

AO commands are not supported.




  

Author: anders.blomdell@control.lth.se (Anders Blomdell)

Status: in development

This driver works, but bulk transfers not implemented. Might be a
starting point for someone else. I found out too late that USB has
too high latencies (>1 ms) for my needs.




  

Author: Prashant Shah <pshah.mumbai@gmail.com>

Status: Stable

Developed at Automation Labs, Chemical Dept., IIT Bombay, India.
Prof. Kannan Moudgalya <kannan@iitb.ac.in>

Notes :
- Dynalog India Pvt. Ltd. does not have a registered PCI Vendor ID and
  they are using the PLX Technlogies Vendor ID since that is the PCI Chip
  used in the card.
- Dynalog India Pvt. Ltd. has provided the internal register specification
  for their cards in their manuals.




  

Author: Anders Gnistrup <ex18@kalman.iau.dtu.dk>

Status: unknown

Digital I/O is not supported.

Configuration options:
  [0] - I/O port base address




  

Author: Frank Mori Hess <fmhess@users.sourceforge.net>

Status: only receive mode works, transmit not supported

Configuration options:
   None.

Manual configuration of supported devices is not supported; they are
configured automatically.

There are some additional hpdi models available from GSC for which
support could be added to this driver.




  

Author: Anne Smorthit <anne.smorthit@sfwte.ch>

Status: works

Configuration options: not applicable, uses PCI auto config

The driver works for analog input and output and digital input and
output. It does not work with interrupts or with the counters. Currently
no support for DMA.

It has 16 single-ended or 8 differential Analogue Input channels with
12-bit resolution.  Ranges : 5V, 10V, +/-5V, +/-10V, 0..20mA and 4..20mA.
Input ranges can be individually programmed for each channel.  Voltage or
current measurement is selected by jumper.

There are 4 x 12-bit Analogue Outputs.  Ranges : 5V, 10V, +/-5V, +/-10V

16 x Digital Inputs, 24V

8 x Digital Outputs, 24V, 1A

4 x 16-bit counters - not implemented




  

Author: Markus Kempf <kempf@matsci.uni-sb.de>

Status: works

Supports the PCI-20001C-1a and PCI-20001C-2a carrier boards. The
-2a version has 32 on-board DIO channels. Three add-on modules
can be added to the carrier board for additional functionality.

Supported add-on modules:
	PCI-20006M-1   1 channel, 16-bit analog output module
	PCI-20006M-2   2 channel, 16-bit analog output module
	PCI-20341M-1A  4 channel, 16-bit analog input module





  

Author: Anders Blomdell <anders.blomdell@control.lth.se>

Status: works

Configuration options:
  None

Manual configuration of comedi devices is not supported by this
driver; supported PCI devices are configured as comedi devices
automatically.

The DSP on the board requires initialization code, which can be
loaded by placing it in /lib/firmware/comedi.  The initialization
code should be somewhere on the media you got with your card.  One
version is available from http://www.comedi.org in the
comedi_nonfree_firmware tarball.  The file is called "jr3pci.idm".




  

Author: Michael Hillmann

Status: tested

Configuration Options: not applicable, uses PCI auto config




  

Author: gg (Guenter Gebhardt <g.gebhardt@meilhaus.com>)

Status: untested

Configuration Options: not applicable, uses PCI auto config

The firmware required by these boards is available in the
comedi_nonfree_firmware tarball available from




  

Author: Michael Hillmann <hillmann@syscongroup.de>

Status: experimental

Configuration options: not applicable, uses PCI auto config





  

Author: Rostislav Lisovy <lisovy@gmail.com>

Status: works

Author: Stanislaw Raczynski <sraczynski@op.pl>

Status: working

The Micro/sys MPC-624 board is based on the LTC2440 24-bit sigma-delta
ADC chip.

Subdevices supported by the driver:
- Analog In:   supported
- Digital I/O: not supported
- LEDs:        not supported
- EEPROM:      not supported

Configuration Options:
  [0] - I/O base address
  [1] - conversion rate
	   Conversion rate   RMS noise	Effective Number Of Bits
	   0	3.52kHz		23uV		17
	   1	1.76kHz		3.5uV		20
	   2	880Hz		2uV		21.3
	   3	440Hz		1.4uV		21.8
	   4	220Hz		1uV		22.4
	   5	110Hz		750uV		22.9
	   6	55Hz		510nV		23.4
	   7	27.5Hz		375nV		24
	   8	13.75Hz		250nV		24.4
	   9	6.875Hz		200nV		24.6
  [2] - voltage range
	   0	-1.01V .. +1.01V
	   1	-10.1V .. +10.1V




  

Author: Anders Blomdell <anders.blomdell@control.lth.se>

Status: works

Configuration Options:
 [0] - I/O port base address
 [1] - IRQ (not used)
 [2] - Number of optional encoder chips installed on board
	  0 = none
	  1 = 2 inputs (Model -2E)
	  2 = 4 inputs (Model -4E)
	  3 = 6 inputs (Model -6E)
	  4 = 8 inputs (Model -8E)




  

Author: David A. Schleef <ds@schleef.org>

Status: works

Configuration Options: not applicable, uses PCI auto config




  

Author: Jon Grierson <jd@renko.co.uk>, Frank Mori Hess <fmhess@users.sourceforge.net>

Status: testing

Configuration Options: not applicable, uses PCI auto config

Based on the PCI-6527 driver by ds.
The interrupt subdevice (subdevice 3) is probably broken for all
boards except maybe the 6514.

This driver previously inverted the outputs on PCI-6513 through to
PCI-6519 and on PXI-6513 through to PXI-6515.  It no longer inverts
outputs on those cards by default as it didn't make much sense.  If
you require the outputs to be inverted on those cards for legacy
reasons, set the module parameter "legacy_invert_outputs=true" when
loading the module, or set "ni_65xx.legacy_invert_outputs=true" on
the kernel command line if the driver is built in to the kernel.




  

Author: J.P. Mellor <jpmellor@rose-hulman.edu>, Herman.Bruyninckx@mech.kuleuven.ac.be, Wim.Meeussen@mech.kuleuven.ac.be, Klaas.Gadeyne@mech.kuleuven.ac.be, Frank Mori Hess <fmhess@users.sourceforge.net>

Status: experimental

Encoders work.  PulseGeneration (both single pulse and pulse train)
works.  Buffered commands work for input but not output.





  

Author: Bart Joris <bjoris@advalvas.be>

Status: unknown

Commands are not supported.





  

Author: Frank Mori Hess

Status: works

Configuration options:
  [0] - I/O port base address
  [1] - IRQ (optional, required for timed conversions)
  [2] - DMA (optional, required for timed conversions)

Yet another driver for obsolete hardware brought to you by Frank Hess.
Testing and debugging help provided by Dave Andruczyk.

If you want to ac couple the board's inputs, use AREF_OTHER.

The only difference in the boards is their master clock frequencies.

References (from ftp://ftp.natinst.com/support/manuals):
  320360.pdf  AT-A2150 User Manual





  

Author: David A. Schleef <ds@schleef.org>

Status: should work

Configuration options:
  [0] - I/O port base address
  [1] - IRQ (unused)
  [2] - DMA (unused)
  [3] - analog output range, set by jumpers on hardware
        0 for -10 to 10V bipolar
        1 for 0V to 10V unipolar




  

Author: ds

Status: works

The driver has 2.6 kernel isapnp support, and will automatically probe for
a supported board if the I/O base is left unspecified with comedi_config.
However, many of the isapnp id numbers are unknown. If your board is not
recognized, please send the output of 'cat /proc/isapnp' (you may need to
modprobe the isa-pnp module for /proc/isapnp to exist) so the id numbers
for your board can be added to the driver.

Otherwise, you can use the isapnptools package to configure your board.
Use isapnp to configure the I/O base and IRQ for the board, and then pass
the same values as parameters in comedi_config. A sample isapnp.conf file
is included in the etc/ directory of Comedilib.

Comedilib includes a utility to autocalibrate these boards. The boards
seem to boot into a state where the all calibration DACs are at one
extreme of their range, thus the default calibration is terrible.
Calibration at boot is strongly encouraged.

To use the extended digital I/O on some of the boards, enable the
8255 driver when configuring the Comedi source tree.

External triggering is supported for some events. The channel index
(scan_begin_arg, etc.) maps to PFI0 - PFI9.

Some of the more esoteric triggering possibilities of these boards are
not supported.




  

Author: Chris R. Baugher <baugher@enteract.com>

Status: unknown

Configuration options:
  [0] - I/O port
  [1] - MIO irq (0 == no irq; or 3,4,5,6,7,9,10,11,12,14,15)
  [2] - DIO irq (0 == no irq; or 3,4,5,6,7,9)
  [3] - DMA1 channel (0 == no DMA; or 5,6,7)
  [4] - DMA2 channel (0 == no DMA; or 5,6,7)
  [5] - a/d mux (0=differential; 1=single)
  [6] - a/d range (0=bipolar10; 1=bipolar5; 2=unipolar10)
  [7] - dac0 range (0=bipolar; 1=unipolar)
  [8] - dac0 reference (0=internal; 1=external)
  [9] - dac0 coding (0=2's comp; 1=straight binary)
  [10] - dac1 range (same as dac0 options)
  [11] - dac1 reference (same as dac0 options)
  [12] - dac1 coding (same as dac0 options)




  

Author: Fred Brooks <nsaspook@nsaspook.com>, based on ni_daq_dio24 by Daniel Vecino Castel <dvecino@able.es>

Status: works

The daqcard-700 appears in Comedi as a  digital I/O subdevice (0) with
16 channels and a analog input subdevice (1) with 16 single-ended channels
or 8 differential channels, and three input ranges.


Digital direction configuration: channels 0-7 output, 8-15 input.


IRQ is assigned but not used.





  

Author: Daniel Vecino Castel <dvecino@able.es>

Status: ?

This is just a wrapper around the 8255.o driver to properly handle
the PCMCIA interface.




  

Author: Frank Mori Hess <fmhess@users.sourceforge.net>

Status: works

Configuration options - ISA boards:
  [0] - I/O port base address
  [1] - IRQ (optional, required for timed or externally triggered
		conversions)
  [2] - DMA channel (optional)

Tested with lab-pc-1200.  For the older Lab-PC+, not all input
ranges and analog references will work, the available ranges/arefs
will depend on how you have configured the jumpers on your board
(see your owner's manual).

Kernel-level ISA plug-and-play support for the lab-pc-1200 boards
has not yet been added to the driver, mainly due to the fact that
I don't know the device id numbers. If you have one of these boards,
please file a bug report at http://comedi.org/ so I can get the
necessary information from you.

The 1200 series boards have onboard calibration dacs for correcting
analog input/output offsets and gains. The proper settings for these
caldacs are stored on the board's eeprom. To read the caldac values
from the eeprom and store them into a file that can be then be used
by comedilib, use the comedi_calibrate program.

The Lab-pc+ has quirky chanlist requirements when scanning multiple
channels. Multiple channel scan sequence must start at highest channel,
then decrement down to channel 0. The rest of the cards can scan down
like lab-pc+ or scan up from channel zero. Chanlists consisting of all
one channel are also legal, and allow you to pace conversions in bursts.

NI manuals:
341309a (labpc-1200 register manual)
320502b (lab-pc+)




  

Author: Frank Mori Hess <fmhess@users.sourceforge.net>

Status: works

Thanks go to Fredrik Lingvall for much testing and perseverance in
helping to debug daqcard-1200 support.

The 1200 series boards have onboard calibration dacs for correcting
analog input/output offsets and gains. The proper settings for these
caldacs are stored on the board's eeprom. To read the caldac values
from the eeprom and store them into a file that can be then be used by
comedilib, use the comedi_calibrate program.

Configuration options: none

The daqcard-1200 has quirky chanlist requirements when scanning multiple
channels. Multiple channel scan sequence must start at highest channel,
then decrement down to channel 0.  Chanlists consisting of all one channel
are also legal, and allow you to pace conversions in bursts.

NI manuals:
  340988a (daqcard-1200)




  

Author: Frank Mori Hess <fmhess@users.sourceforge.net>

Status: works

This is the PCI-specific support split off from the ni_labpc driver.

Configuration Options: not applicable, uses PCI auto config

NI manuals:
340914a (pci-1200)




  

Author: ds

Status: works

See the notes in the ni_atmio.o driver.




  

Author: ds

Status: works

The DIO32HS board appears as one subdevice, with 32 channels. Each
channel is individually I/O configurable. The channel order is 0=A0,
1=A1, 2=A2, ... 8=B0, 16=C0, 24=D0. The driver only supports simple
digital I/O; no handshaking is supported.

DMA mostly works for the PCI-DIO32HS, but only in timed input mode.

The PCI-DIO-32HS/PCI-6533 has a configurable external trigger. Setting
scan_begin_arg to 0 or CR_EDGE triggers on the leading edge. Setting
scan_begin_arg to CR_INVERT or (CR_EDGE | CR_INVERT) triggers on the
trailing edge.

This driver could be easily modified to support AT-MIO32HS and AT-MIO96.

The PCI-6534 requires a firmware upload after power-up to work, the
firmware data and instructions for loading it with comedi_config
it are contained in the comedi_nonfree_firmware tarball available from




  

Author: ds, John Hallen, Frank Mori Hess, Rolf Mueller, Herbert Peremans, Herman Bruyninckx, Terry Barnaby

Status: works

These boards are almost identical to the AT-MIO E series, except that
they use the PCI bus instead of ISA (i.e., AT). See the notes for the
ni_atmio.o driver for additional information about these boards.

Autocalibration is supported on many of the devices, using the
comedi_calibrate (or comedi_soft_calibrate for m-series) utility.
M-Series boards do analog input and analog output calibration entirely
in software. The software calibration corrects the analog input for
offset, gain and nonlinearity. The analog outputs are corrected for
offset and gain. See the comedilib documentation on
comedi_get_softcal_converter() for more information.

By default, the driver uses DMA to transfer analog input data to
memory.  When DMA is enabled, not all triggering features are
supported.

Digital I/O may not work on 673x.

Note that the PCI-6143 is a simultaineous sampling device with 8
convertors. With this board all of the convertors perform one
simultaineous sample during a scan interval. The period for a scan
is used for the convert time in a Comedi cmd. The convert trigger
source is normally set to TRIG_NOW by default.

The RTSI trigger bus is supported on these cards on subdevice 10.
See the comedilib documentation for details.

Information (number of channels, bits, etc.) for some devices may be
incorrect. Please check this and submit a bug if there are problems
for your device.

SCXI is probably broken for m-series boards.





  

Author: Luca Ellero <luca.ellero@brickedbrain.com>

Status: works

Configuration Options:
none




  

Author: David A. Schleef <ds@schleef.org> Janne Jalkanen <jalkanen@cs.hut.fi> Eric Bunn <ebu@cs.hut.fi>

Status: mostly complete

Configuration Options:
  [0] - I/O port base
  [1] - IRQ, optional




  

Author: Michal Dobes <dobes@tesnet.cz>

Status: untested

Configuration options:
  [0] - IO Base
  [1] - IRQ (not supported)
  [2] - number of DIO (pcl722 and acl7122 boards)
	   0, 144: 144 DIO configuration
	   1,  96:  96 DIO configuration




  

Author: David A. Schleef <ds@schleef.org>

Status: untested

Configuration Options:
  [0]  - IO Base
  [1]  - IRQ (ACL-6126 only)
  [2]  - D/A output range for channel 0
  [3]  - D/A output range for channel 1

Boards with > 2 analog output channels:
  [4]  - D/A output range for channel 2
  [5]  - D/A output range for channel 3
  [6]  - D/A output range for channel 4
  [7]  - D/A output range for channel 5

Boards with > 6 analog output channels:
  [8]  - D/A output range for channel 6
  [9]  - D/A output range for channel 7
  [10] - D/A output range for channel 8
  [11] - D/A output range for channel 9
  [12] - D/A output range for channel 10
  [13] - D/A output range for channel 11

For PCL-726 the D/A output ranges are:
  0: 0-5V, 1: 0-10V, 2: +/-5V, 3: +/-10V, 4: 4-20mA, 5: unknown

For PCL-727:
  0: 0-5V, 1: 0-10V, 2: +/-5V, 3: 4-20mA

For PCL-728 and ACL-6128:
  0: 0-5V, 1: 0-10V, 2: +/-5V, 3: +/-10V, 4: 4-20mA, 5: 0-20mA

For ACL-6126:
  0: 0-5V, 1: 0-10V, 2: +/-5V, 3: +/-10V, 4: 4-20mA




  

Author: José Luis Sánchez (jsanchezv@teleline.es)

Status: untested

Configuration options:
  [0] - I/O port base

Interrupts are not supported.
The ACL-7130 card has an 8254 timer/counter not supported by this driver.




  

Author: Michal Dobes <dobes@tesnet.cz>

Status: works (I hope. My board fire up under my hands and I cann't test all features.)

This driver supports insn and cmd interfaces. Some boards support only insn
because their hardware don't allow more (PCL-813/B, ACL-8113, ISO-813).
Data transfer over DMA is supported only when you measure only one
channel, this is too hardware limitation of these boards.

Options for PCL-812:
  [0] - IO Base
  [1] - IRQ  (0=disable, 2, 3, 4, 5, 6, 7; 10, 11, 12, 14, 15)
  [2] - DMA  (0=disable, 1, 3)
  [3] - 0=trigger source is internal 8253 with 2MHz clock
        1=trigger source is external
  [4] - 0=A/D input range is +/-10V
	   1=A/D input range is +/-5V
	   2=A/D input range is +/-2.5V
	   3=A/D input range is +/-1.25V
	   4=A/D input range is +/-0.625V
	   5=A/D input range is +/-0.3125V
  [5] - 0=D/A outputs 0-5V  (internal reference -5V)
	   1=D/A outputs 0-10V (internal reference -10V)
	   2=D/A outputs unknown (external reference)

Options for PCL-812PG, ACL-8112PG:
  [0] - IO Base
  [1] - IRQ  (0=disable, 2, 3, 4, 5, 6, 7; 10, 11, 12, 14, 15)
  [2] - DMA  (0=disable, 1, 3)
  [3] - 0=trigger source is internal 8253 with 2MHz clock
	   1=trigger source is external
  [4] - 0=A/D have max +/-5V input
	   1=A/D have max +/-10V input
  [5] - 0=D/A outputs 0-5V  (internal reference -5V)
	   1=D/A outputs 0-10V (internal reference -10V)
	   2=D/A outputs unknown (external reference)

Options for ACL-8112DG/HG, A-822PGL/PGH, A-823PGL/PGH, ACL-8216, A-826PG:
  [0] - IO Base
  [1] - IRQ  (0=disable, 2, 3, 4, 5, 6, 7; 10, 11, 12, 14, 15)
  [2] - DMA  (0=disable, 1, 3)
  [3] - 0=trigger source is internal 8253 with 2MHz clock
	   1=trigger source is external
  [4] - 0=A/D channels are S.E.
	   1=A/D channels are DIFF
  [5] - 0=D/A outputs 0-5V  (internal reference -5V)
	   1=D/A outputs 0-10V (internal reference -10V)
	   2=D/A outputs unknown (external reference)

Options for A-821PGL/PGH:
  [0] - IO Base
  [1] - IRQ  (0=disable, 2, 3, 4, 5, 6, 7)
  [2] - 0=A/D channels are S.E.
	   1=A/D channels are DIFF
  [3] - 0=D/A output 0-5V  (internal reference -5V)
	   1=D/A output 0-10V (internal reference -10V)

Options for A-821PGL-NDA:
  [0] - IO Base
  [1] - IRQ  (0=disable, 2, 3, 4, 5, 6, 7)
  [2] - 0=A/D channels are S.E.
	   1=A/D channels are DIFF

Options for PCL-813:
  [0] - IO Base

Options for PCL-813B:
  [0] - IO Base
  [1] - 0= bipolar inputs
	   1= unipolar inputs

Options for ACL-8113, ISO-813:
  [0] - IO Base
  [1] - 0= 10V bipolar inputs
	   1= 10V unipolar inputs
	   2= 20V bipolar inputs
	   3= 20V unipolar inputs




  

Author: Juan Grigera <juan@grigera.com.ar>

Status: works

PCL 816 and 814B have 16 SE/DIFF ADCs, 16 DACs, 16 DI and 16 DO.
Differences are at resolution (16 vs 12 bits).

The driver support AI command mode, other subdevices not written.

Analog output and digital input and output are not supported.

Configuration Options:
  [0] - IO Base
  [1] - IRQ	(0=disable, 2, 3, 4, 5, 6, 7)
  [2] - DMA	(0=disable, 1, 3)
  [3] - 0, 10=10MHz clock for 8254
	       1= 1MHz clock for 8254




  

Author: Michal Dobes <dobes@tesnet.cz>

Status: works

All cards have 16 SE/8 DIFF ADCs, one or two DACs, 16 DI and 16 DO.
Differences are only at maximal sample speed, range list and FIFO
support.
The driver support AI mode 0, 1, 3 other subdevices (AO, DI, DO) support
only mode 0. If DMA/FIFO/INT are disabled then AI support only mode 0.
PCL-818HD and PCL-818HG support 1kword FIFO. Driver support this FIFO
but this code is untested.
A word or two about DMA. Driver support DMA operations at two ways:
1) DMA uses two buffers and after one is filled then is generated
   INT and DMA restart with second buffer. With this mode I'm unable run
   more that 80Ksamples/secs without data dropouts on K6/233.
2) DMA uses one buffer and run in autoinit mode and the data are
   from DMA buffer moved on the fly with 2kHz interrupts from RTC.
   This mode is used if the interrupt 8 is available for allocation.
   If not, then first DMA mode is used. With this I can run at
   full speed one card (100ksamples/secs) or two cards with
   60ksamples/secs each (more is problem on account of ISA limitations).
   To use this mode you must have compiled  kernel with disabled
   "Enhanced Real Time Clock Support".
   Maybe you can have problems if you use xntpd or similar.
   If you've data dropouts with DMA mode 2 then:
    a) disable IDE DMA
    b) switch text mode console to fb.

 Options for PCL-818L:
 [0] - IO Base
 [1] - IRQ        (0=disable, 2, 3, 4, 5, 6, 7)
 [2] - DMA        (0=disable, 1, 3)
 [3] - 0, 10=10MHz clock for 8254
           1= 1MHz clock for 8254
 [4] - 0,  5=A/D input  -5V.. +5V
       1, 10=A/D input -10V..+10V
 [5] - 0,  5=D/A output 0-5V  (internal reference -5V)
       1, 10=D/A output 0-10V (internal reference -10V)
       2    =D/A output unknown (external reference)

 Options for PCL-818, PCL-818H:
 [0] - IO Base
 [1] - IRQ        (0=disable, 2, 3, 4, 5, 6, 7)
 [2] - DMA        (0=disable, 1, 3)
 [3] - 0, 10=10MHz clock for 8254
           1= 1MHz clock for 8254
 [4] - 0,  5=D/A output 0-5V  (internal reference -5V)
       1, 10=D/A output 0-10V (internal reference -10V)
       2    =D/A output unknown (external reference)

 Options for PCL-818HD, PCL-818HG:
 [0] - IO Base
 [1] - IRQ        (0=disable, 2, 3, 4, 5, 6, 7)
 [2] - DMA/FIFO  (-1=use FIFO, 0=disable both FIFO and DMA,
                   1=use DMA ch 1, 3=use DMA ch 3)
 [3] - 0, 10=10MHz clock for 8254
           1= 1MHz clock for 8254
 [4] - 0,  5=D/A output 0-5V  (internal reference -5V)
       1, 10=D/A output 0-10V (internal reference -10V)
       2    =D/A output unknown (external reference)

 Options for PCL-718:
 [0] - IO Base
 [1] - IRQ        (0=disable, 2, 3, 4, 5, 6, 7)
 [2] - DMA        (0=disable, 1, 3)
 [3] - 0, 10=10MHz clock for 8254
           1= 1MHz clock for 8254
 [4] -     0=A/D Range is +/-10V
           1=             +/-5V
           2=             +/-2.5V
           3=             +/-1V
           4=             +/-0.5V
           5=             user defined bipolar
           6=             0-10V
           7=             0-5V
           8=             0-2V
           9=             0-1V
          10=             user defined unipolar
 [5] - 0,  5=D/A outputs 0-5V  (internal reference -5V)
       1, 10=D/A outputs 0-10V (internal reference -10V)
           2=D/A outputs unknown (external reference)
 [6] - 0, 60=max  60kHz A/D sampling
       1,100=max 100kHz A/D sampling (PCL-718 with Option 001 installed)




  

Author: Drew Csillag <drew_csillag@yahoo.com>

Status: tested

This is driver for digital I/O boards PCM-3724 with 48 DIO.
It needs 8255.o for operations and only immediate mode is supported.
See the source for configuration details.

Copy/pasted/hacked from pcm724.c

Configuration Options:
  [0] - I/O port base address




  

Author: ds

Status: untested

This driver was written on a bet that I couldn't write a driver
in less than 2 hours.  I won the bet, but never got paid.  =(

Configuration options:
  [0] - I/O port base
  [1] - IRQ (unused)
  [2] - Analog input reference (must match jumpers)
	   0 = single-ended (16 channels)
	   1 = differential (8 channels)
  [3] - Analog input encoding (must match jumpers)
	   0 = straight binary (0-5V input range)
	   1 = two's complement (+-10V input range)




  

Author: Calin Culianu <calin@ajvar.org>

Status: works

A driver for the relatively straightforward-to-program PCM-D/A-12.
This board doesn't support commands, and the only way to set its
analog output range is to jumper the board. As such,
comedi_data_write() ignores the range value specified.

The board uses 16 consecutive I/O addresses starting at the I/O port
base address. Each address corresponds to the LSB then MSB of a
particular channel from 0-7.

Note that the board is not ISA-PNP capable and thus needs the I/O
port comedi_config parameter.

Note that passing a nonzero value as the second config option will
enable "simultaneous xfer" mode for this board, in which AO writes
will not take effect until a subsequent read of any AO channel. This
is so that one can speed up programming by preloading all AO registers
with values before simultaneously setting them to take effect with one
read command.

Configuration Options:
  [0] - I/O port base address
  [1] - Do Simultaneous Xfer (see description)




  

Author: Calin Culianu <calin@ajvar.org>

Status: works

A driver for the PCM-MIO multifunction board from Winsystems. This
is a PC-104 based I/O board. It contains four subdevices:

	subdevice 0 - 16 channels of 16-bit AI
	subdevice 1 - 8 channels of 16-bit AO
	subdevice 2 - first 24 channels of the 48 channel of DIO
			(with edge-triggered interrupt support)
	subdevice 3 - last 24 channels of the 48 channel DIO
			(no interrupt support for this bank of channels)

Some notes:

Synchronous reads and writes are the only things implemented for analog
input and output. The hardware itself can do streaming acquisition, etc.

Asynchronous I/O for the DIO subdevices *is* implemented, however! They
are basically edge-triggered interrupts for any configuration of the
channels in subdevice 2.

Also note that this interrupt support is untested.

A few words about edge-detection IRQ support (commands on DIO):

To use edge-detection IRQ support for the DIO subdevice, pass the IRQ
of the board to the comedi_config command. The board IRQ is not jumpered
but rather configured through software, so any IRQ from 1-15 is OK.

Due to the genericity of the comedi API, you need to create a special
comedi_command in order to use edge-triggered interrupts for DIO.

Use comedi_commands with TRIG_NOW.  Your callback will be called each
time an edge is detected on the specified DIO line(s), and the data
values will be two sample_t's, which should be concatenated to form
one 32-bit unsigned int. This value is the mask of channels that had
edges detected from your channel list. Note that the bits positions
in the mask correspond to positions in your chanlist when you
specified the command and *not* channel id's!

To set the polarity of the edge-detection interrupts pass a nonzero value
for either CR_RANGE or CR_AREF for edge-up polarity, or a zero
value for both CR_RANGE and CR_AREF if you want edge-down polarity.

Configuration Options:
  [0] - I/O port base address
  [1] - IRQ (optional -- for edge-detect interrupt support only,
		leave out if you don't need this feature)




  

Author: Calin Culianu <calin@ajvar.org>

Status: works

A driver for the relatively straightforward-to-program PCM-UIO48A and
PCM-UIO96A boards from Winsystems. These boards use either one or two
(in the 96-DIO version) WS16C48 ASIC HighDensity I/O Chips (HDIO). This
chip is interesting in that each I/O line is individually programmable
for INPUT or OUTPUT (thus comedi_dio_config can be done on a per-channel
basis). Also, each chip supports edge-triggered interrupts for the first
24 I/O lines. Of course, since the 96-channel version of the board has
two ASICs, it can detect polarity changes on up to 48 I/O lines. Since
this is essentially an (non-PnP) ISA board, I/O Address and IRQ selection
are done through jumpers on the board. You need to pass that information
to this driver as the first and second comedi_config option, respectively.
Note that the 48-channel version uses 16 bytes of IO memory and the 96-
channel version uses 32-bytes (in case you are worried about conflicts).
The 48-channel board is split into two 24-channel comedi subdevices. The
96-channel board is split into 4 24-channel DIO subdevices.

Note that IRQ support has been added, but it is untested.

To use edge-detection IRQ support, pass the IRQs of both ASICS (for the
96 channel version) or just 1 ASIC (for 48-channel version). Then, use
comedi_commands with TRIG_NOW. Your callback will be called each time an
edge is triggered, and the data values will be two sample_t's, which
should be concatenated to form one 32-bit unsigned int.  This value is
the mask of channels that had edges detected from your channel list. Note
that the bits positions in the mask correspond to positions in your
chanlist when you specified the command and *not* channel id's!

To set the polarity of the edge-detection interrupts pass a nonzero value
for either CR_RANGE or CR_AREF for edge-up polarity, or a zero value for
both CR_RANGE and CR_AREF if you want edge-down polarity.

In the 48-channel version:

On subdev 0, the first 24 channels channels are edge-detect channels.

In the 96-channel board you have the following channels that can do edge

subdev 0, channels 0-24  (first 24 channels of 1st ASIC)
subdev 2, channels 0-24  (first 24 channels of 2nd ASIC)

Configuration Options:
 [0] - I/O port base address
 [1] - IRQ (for first ASIC, or first 24 channels)
 [2] - IRQ (for second ASIC, pcmuio96 only - IRQ for chans 48-72
            can be the same as first irq!)




  

Author: Brent Baccala <baccala@freesoft.org>

Status: works

Author: Dan Christian

Status: Works. Only tested on DM7520-8. Not SMP safe.

Configuration options: not applicable, uses PCI auto config




  

Author: David A. Schleef <ds@schleef.org>

Status: unknown

Configuration options:
  [0] - I/O port base address
  [1] - IRQ (not supported / unused)
  [2] - A/D mux/reference (number of channels)
	   0 = differential
	   1 = pseudodifferential (common)
	   2 = single-ended
  [3] - A/D range
	   0 = [-10,10]
	   1 = [-5,5]
	   2 = [0,10]
  [4] - A/D encoding
	   0 = two's complement
	   1 = straight binary
  [5] - DAC 0 range
	   0 = [-10,10]
	   1 = [0,10]
  [6] - DAC 0 encoding
	   0 = two's complement
	   1 = straight binary
  [7] - DAC 1 range (same as DAC 0)
  [8] - DAC 1 encoding (same as DAC 0)




  

Author: Anders Blomdell <anders.blomdell@control.lth.se>

Status: works

Configuration Options:
  [0] - i/o base
  [1] - unused
  [2,4,6,8,10,12,14,16] - dac#[0-7]  0=two's comp, 1=straight
  [3,5,7,9,11,13,15,17] - dac#[0-7]  0=bipolar, 1=unipolar




  

Author: Richie Everett Wang <everett.wang@everteq.com>

Status: experimental

Encoder works
Analog input works
Analog output works
PWM output works
Commands are not supported yet.

Configuration Options:
  [0] - I/O port base address




  

Author: Richie Everett Wang &lt;everett.wang&#64;everteq.com&gt;

Status: experimental

Configuration options: not applicable, uses PCI auto config

INSN_CONFIG instructions:
  analog input:
   none

  analog output:
   none

  digital channel:
   s626 has 3 dio subdevices (2,3 and 4) each with 16 i/o channels
   supported configuration options:
   INSN_CONFIG_DIO_QUERY
   COMEDI_INPUT
   COMEDI_OUTPUT

  encoder:
   Every channel must be configured before reading.

  Example code

   insn.insn=INSN_CONFIG;   //configuration instruction
   insn.n=1;                //number of operation (must be 1)
   insn.data=&initialvalue; //initial value loaded into encoder
                            //during configuration
   insn.subdev=5;           //encoder subdevice
   insn.chanspec=CR_PACK(encoder_channel,0,AREF_OTHER); //encoder_channel
                                                        //to configure

   comedi_do_insn(cf,&insn); //executing configuration




  

Author: Robert Schwebel <robert@schwebel.de>

Status: unknown

Author: Bernd Porr <mail@berndporr.me.uk>

Status: Stable

Connection scheme for the counter at the digital port:
0=/CLK0, 1=UP/DOWN0, 2=RESET0, 4=/CLK1, 5=UP/DOWN1, 6=RESET1.
The sampling rate of the counter is approximately 500Hz.

Note that under USB2.0 the length of the channel list determines
the max sampling rate. If you sample only one channel you get 8kHz
sampling rate. If you sample two channels you get 4kHz and so on.




  

Author: Bernd Porr <mail@berndporr.me.uk>

Status: stable

Author: Bernd Porr <mail@berndporr.me.uk>

Status: stable

Author: Manuel Gebele <forensixs@gmx.de>

Status: works

Author: ds

Status: works

The classic in digital I/O.  The 8255 appears in Comedi as a single
digital I/O subdevice with 24 channels.  The channel 0 corresponds
to the 8255's port A, bit 0; channel 23 corresponds to port C, bit
7.  Direction configuration is done in blocks, with channels 0-7,
8-15, 16-19, and 20-23 making up the 4 blocks.  The only 8255 mode
supported is mode 0.

You should enable compilation this driver if you plan to use a board
that has an 8255 chip.  For multifunction boards, the main driver will
configure the 8255 subdevice automatically.

This driver also works independently with ISA and PCI cards that
directly map the 8255 registers to I/O ports, including cards with
multiple 8255 chips.  To configure the driver for such a card, the
option list should be a list of the I/O port bases for each of the
8255 chips.  For example,

  comedi_config /dev/comedi0 8255 0x200,0x204,0x208,0x20c

Note that most PCI 8255 boards do NOT work with this driver, and
need a separate driver as a wrapper.  For those that do work, the
I/O port base address can be found in the output of 'lspci -v'.




  

Author: José Luis Sánchez (jsanchezv@teleline.es)

Status: testing

Author: nsyeow <nsyeow@pd.jaring.my>

Status: untested

Configuration Options:
  none

The driver should work for PCI-6208V, PCI-6208A and PCI-6216V, but all
devices will be treated as a PCI-6216V.

For PCI-6208V and PCI-6208A, only AO channels 0 to 7 are connected and
AO channels 8 to 15 will behave as "phantom" outputs.

The current output ranges for PCI-6208A are not supported.  Only Comedi
sample values 0x8000 to 0xffff should be written to the AO channels on a
PCI-6208A.  Its voltage to current daughter board (EXP-8A) only supports
an input range of 0 to 10 volts and negative voltages may damage the
board.  Comedi sample values 0x0000 to 0x7fff would produce negative
voltages from -10 to 0 volts.





  

Author: David Fernandez <dfcastelao@gmail.com>

Status: experimental

Configuration Options:
  [0] - PCI bus of device (optional)
  [1] - PCI slot of device (optional)
  If bus/slot is not specified, the first supported
  PCI device found will be used.




  

Author: Ian Abbott <abbotti@mev.co.uk>

Status: works

The driver assumes that 3 PCI-7251 modules are fitted to the PCI-7250,
giving 32 channels of relay outputs and 32 channels of isolated digital
inputs.  That is also the case for the LPCI-7250 and LPCIe-7250 cards
although they do not physically support the PCI-7251 modules.

Not fitting the PCI-7251 modules shouldn't do any harm, but the extra
inputs and relay outputs won't work!

Configuration Options:
  [0] - PCI bus of device (optional)
  [1] - PCI slot of device (optional)
  If bus/slot is not specified, the first supported
  PCI device found will be used.




  

Author: Jon Grierson <jd@renko.co.uk>

Status: testing

Configuration Options:
  [0] - PCI bus of device (optional)
  [1] - PCI slot of device (optional)
  If bus/slot is not specified, the first supported
  PCI device found will be used.




  

Author: Michel Lachaine <mike@mikelachaine.ca>

Status: experimental

Configuration Options:
  [0] - PCI bus of device (optional)
  [1] - PCI slot of device (optional)
  If bus/slot is not specified, the first supported
  PCI device found will be used.




  

Author: Michel Lachaine <mike@mikelachaine.ca>

Status: experimental

Configuration Options:
  [0] - PCI bus of device (optional)
  [1] - PCI slot of device (optional)
  If bus/slot is not specified, the first supported
  PCI device found will be used.




  

Author: Emmanuel Pacaud <emmanuel.pacaud@univ-poitiers.fr>

Status: experimental

  - ai_insn read
  - ao_insn read/write
  - di_insn read
  - do_insn read/write
  - ai_do_cmd mode with the following sources:

    - start_src 		TRIG_NOW
    - scan_begin_src 		TRIG_FOLLOW	TRIG_TIMER	TRIG_EXT
    - convert_src				TRIG_TIMER	TRIG_EXT
    - scan_end_src		TRIG_COUNT
    - stop_src			TRIG_COUNT	TRIG_NONE

    The scanned channels must be consecutive and start from 0. They must
    all have the same range and aref.

Configuration options:

    [0] - PCI bus number (optional)
    [1] - PCI slot number (optional)

    If bus/slot is not specified, the first available PCI
    device will be used.




  

Author: Pascal Berthou <berthou@laas.fr> Emmanuel Pacaud <emmanuel.pacaud@univ-poitiers.fr>

Status: experimental

  - ai_insn read
  - ao_insn read/write
  - di_insn read
  - do_insn read/write

  Following command mode are not tested
  - ai_do_cmd mode with the following sources:

    - start_src 		TRIG_NOW
    - scan_begin_src 		TRIG_FOLLOW	TRIG_TIMER	TRIG_EXT
    - convert_src				TRIG_TIMER	TRIG_EXT
    - scan_end_src		TRIG_COUNT
    - stop_src			TRIG_COUNT	TRIG_NONE

    The scanned channels must be consecutive and start from 0. They must
    all have the same range and aref.

Configuration options:

    [0] - PCI bus number (optional)
    [1] - PCI slot number (optional)

    If bus/slot is not specified, the first available PCI
    device will be used.




  

Author: Michal Dobes <dobes@tesnet.cz>

Status: works

This driver supports AI, AO, DI and DO subdevices.
AI subdevice supports cmd and insn interface,
other subdevices support only insn interface.
For AI:
- If cmd->scan_begin_src=TRIG_EXT then trigger input is TGIN (pin 46).
- If cmd->convert_src=TRIG_EXT then trigger input is EXTTRG (pin 44).
- If cmd->start_src/stop_src=TRIG_EXT then trigger input is TGIN (pin 46).
- It is not neccessary to have cmd.scan_end_arg=cmd.chanlist_len but
  cmd.scan_end_arg modulo cmd.chanlist_len must by 0.
- If return value of cmdtest is 5 then you've bad channel list
  (it isn't possible mixture S.E. and DIFF inputs or bipolar and unipolar
  ranges).

There are some hardware limitations:
a) You cann't use mixture of unipolar/bipoar ranges or differencial/single
   ended inputs.
b) DMA transfers must have the length aligned to two samples (32 bit),
   so there is some problems if cmd->chanlist_len is odd. This driver tries
   bypass this with adding one sample to the end of the every scan and discard
   it on output but this cann't be used if cmd->scan_begin_src=TRIG_FOLLOW
   and is used flag TRIG_WAKE_EOS, then driver switch to interrupt driven mode
   with interrupt after every sample.
c) If isn't used DMA then you can use only mode where
   cmd->scan_begin_src=TRIG_FOLLOW.

Configuration options:
  [0] - PCI bus of device (optional)
  [1] - PCI slot of device (optional)
          If bus/slot is not specified, then first available PCI
          card will be used.
  [2] - 0= standard 8 DIFF/16 SE channels configuration
        n= external multiplexer connected, 1<=n<=256
  [3] - 0=autoselect DMA or EOC interrupts operation
        1=disable DMA mode
        3=disable DMA and INT, only insn interface will work
  [4] - sample&hold signal - card can generate signal for external S&H board
        0=use SSHO (pin 45) signal is generated in onboard hardware S&H logic
        0!=use ADCHN7 (pin 23) signal is generated from driver, number
           say how long delay is requested in ns and sign polarity of the hold
           (in this case external multiplexor can serve only 128 channels)
  [5] - 0=stop measure on all hardware errors
        2|=ignore ADOR - A/D Overrun status
	8|=ignore Bover - A/D Burst Mode Overrun status
	256|=ignore nFull - A/D FIFO Full status




  

Author: jeremy theler <thelerg@ib.cnea.gov.ar>

Status: works

Driver for the acquisition card ADQ12-B (without any add-on).

 - Analog input is subdevice 0 (16 channels single-ended or 8 differential)
 - Digital input is subdevice 1 (5 channels)
 - Digital output is subdevice 1 (8 channels)
 - The PACER is not supported in this version

If you do not specify any options, they will default to

  # comedi_config /dev/comedi0 adq12b 0x300,0,0

  option 1: I/O base address. The following table is provided as a help
   of the hardware jumpers.

         address            jumper JADR
          0x300                 1 (factory default)
          0x320                 2
          0x340                 3
          0x360                 4
          0x380                 5
          0x3A0                 6

  option 2: unipolar/bipolar ADC selection: 0 -> bipolar, 1 -> unipolar

        selection         comedi_config option            JUB
         bipolar                0                         2-3 (factory default)
         unipolar               1                         1-2

  option 3: single-ended/differential AI selection: 0 -> SE, 1 -> differential

        selection         comedi_config option     JCHA    JCHB
       single-ended             0                  1-2     1-2 (factory default) 
       differential             1                  2-3     2-3


   written by jeremy theler <thelerg@ib.cnea.gov.ar>

   instituto balseiro
   comision nacional de energia atomica
   universidad nacional de cuyo
   argentina

   21-feb-2008
     + changed supported devices string (missused the [] and ())

   13-oct-2007
     + first try




  

Author: Michal Dobes <dobes@tesnet.cz>

Status: works

This driver supports AI, AO, DI and DO subdevices.
AI subdevice supports cmd and insn interface,
other subdevices support only insn interface.

The PCI-1710 and PCI-1710HG have the same PCI device ID, so the
driver cannot distinguish between them, as would be normal for a
PCI driver.

Configuration options:
  [0] - PCI bus of device (optional)
  [1] - PCI slot of device (optional)
          If bus/slot is not specified, the first available PCI
          device will be used.




  

Author: yonggang <rsmgnu@gmail.com>, Ian Abbott <abbotti@mev.co.uk>

Status: works

Configuration Options:
  [0] - PCI bus of device (optional)
  [1] - PCI slot of device (optional)

  If bus/slot is not specified, the first supported
  PCI device found will be used.

Subdevice 0 is 8-channel AO, 16-bit, range +/- 10 V.

Subdevice 1 is 16-channel DIO.  The channels are configurable as input or
output in 2 groups (0 to 7, 8 to 15).  Configuring any channel implicitly
configures all channels in the same group.


1. Add the two milliamp ranges to the AO subdevice (0 to 20 mA, 4 to 20 mA).
2. Read the initial ranges and values of the AO subdevice at start-up instead
   of reinitializing them.
3. Implement calibration.




  

Author: Frank Mori Hess <fmh6jj@gmail.com>

Status: works

Configuration Options:
  [0] - PCI bus of device (optional)
  [1] - PCI slot of device (optional)

  If bus/slot is not specified, the first supported
  PCI device found will be used.


Subdevice 0 is the analog output.
Subdevice 1 is the offset calibration for the analog output.
Subdevice 2 is the gain calibration for the analog output.

The calibration offset and gains have quite a large effect on the
analog output, so it is possible to adjust the analog output to
have an output range significantly different from the board's
nominal output ranges. For a calibrated +/-10V range, the analog
output's offset will be set somewhere near mid-range (0x2000) and
its gain will be near maximum (0x3fff).

There is really no difference between the board's documented 0-20mA
versus 4-20mA output ranges. To pick one or the other is simply a
matter of adjusting the offset and gain calibration until the board
outputs in the desired range.

Subdevice 0 supports a synchronized output mode.  In this mode,
values written to the analog output channels will not appear on the
outputs until synchronized output is triggered.

An INSN_CONFIG_ARM configuration instruction is used to enable
synchronized output mode and optionally trigger synchronized output.
If data[1] is non-zero, synchronized output will be triggered.

    comedi_insn insn;
    lsampl_t data[2];
    int ret;
    memset(&insn, 0, sizeof(insn));
    insn.insn = INSN_CONFIG;
    insn.subdev = 0;
    insn.chanspec = 0;
    insn.data = data;
    insn.n = 2;
    data[0] = INSN_CONFIG_ARM;
    data[1] = trigger; // 0 = only enable; 1 = trigger now
    ret = comedi_do_insn(d, &insn);

An INSN_CONFIG_DISARM configuration instruction is used to disable
synchronized output mode.

    comedi_insn insn;
    lsampl_t data[1];
    int ret;
    memset(&insn, 0, sizeof(insn));
    insn.insn = INSN_CONFIG;
    insn.subdev = 0;
    insn.chanspec = 0;
    insn.data = data;
    insn.n = 1;
    data[0] = INSN_CONFIG_DISARM;
    ret = comedi_do_insn(d, &insn);




  

Author: Michal Dobes <dobes@tesnet.cz>

Status: untested

This driver supports now only insn interface for DI/DO/DIO.

Configuration options:
  [0] - PCI bus of device (optional)
  [1] - PCI slot of device (optional)
          If bus/slot is not specified, the first available PCI
          device will be used.




  

Author: Pablo Mejia <pablo.mejia@cctechnol.com>

Status: experimental

Configuration Options:
  [0] - I/O port base address


  Only synchronous operations are supported.




  

Author: Zachary Ware <zach.ware@cctechnol.com>

Status: experimental

Configuration Options:
  [0] - I/O port base address




  

Author: Ian Abbott <abbotti@mev.co.uk>

Status: works

Configuration options - PC212E, PC214E, PC215E, PC218E, PC272E:
  [0] - I/O port base address
  [1] - IRQ (optional, but commands won't work without it)

Configuration options - PCI215, PCIe215, PCIe236, PCI272, PCIe296:
  [0] - PCI bus of device (optional)
  [1] - PCI slot of device (optional)
  If bus/slot is not specified, the first available PCI device will
  be used.

Passing a zero for an option is the same as leaving it unspecified.

SUBDEVICES

                    PC212E         PC214E      PC215E/PCI215
                 -------------  -------------  -------------
  Subdevices           6              4              5
   0                 PPI-X          PPI-X          PPI-X
   1                 CTR-Y1         PPI-Y          PPI-Y
   2                 CTR-Y2         CTR-Z1*        CTR-Z1
   3                 CTR-Z1       INTERRUPT*       CTR-Z2
   4                 CTR-Z2                      INTERRUPT
   5               INTERRUPT

                    PCIe215        PC218E         PCIe236
                 -------------  -------------  -------------
  Subdevices           8              7              8
   0                 PPI-X          CTR-X1         PPI-X
   1                 UNUSED         CTR-X2         UNUSED
   2                 PPI-Y          CTR-Y1         UNUSED
   3                 UNUSED         CTR-Y2         UNUSED
   4                 CTR-Z1         CTR-Z1         CTR-Z1
   5                 CTR-Z2         CTR-Z2         CTR-Z2
   6                 TIMER        INTERRUPT        TIMER
   7               INTERRUPT                     INTERRUPT

                 PC272E/PCI272     PCIe296
                 -------------  -------------
  Subdevices           4              8
   0                 PPI-X          PPI-X1
   1                 PPI-Y          PPI-X2
   2                 PPI-Z          PPI-Y1
   3               INTERRUPT        PPI-Y2
   4                                CTR-Z1
   5                                CTR-Z2
   6                                TIMER
   7                              INTERRUPT

Each PPI is a 8255 chip providing 24 DIO channels.  The DIO channels
are configurable as inputs or outputs in four groups:

  Port A  - channels  0 to  7
  Port B  - channels  8 to 15
  Port CL - channels 16 to 19
  Port CH - channels 20 to 23

Only mode 0 of the 8255 chips is supported.

Each CTR is a 8254 chip providing 3 16-bit counter channels.  Each
channel is configured individually with INSN_CONFIG instructions.  The
specific type of configuration instruction is specified in data[0].
Some configuration instructions expect an additional parameter in
data[1]; others return a value in data[1].  The following configuration
instructions are supported:

  INSN_CONFIG_SET_COUNTER_MODE.  Sets the counter channel's mode and
    BCD/binary setting specified in data[1].

  INSN_CONFIG_8254_READ_STATUS.  Reads the status register value for the
    counter channel into data[1].

  INSN_CONFIG_SET_CLOCK_SRC.  Sets the counter channel's clock source as
    specified in data[1] (this is a hardware-specific value).  Not
    supported on PC214E.  For the other boards, valid clock sources are
    0 to 7 as follows:

      0.  CLK n, the counter channel's dedicated CLK input from the SK1
        connector.  (N.B. for other values, the counter channel's CLKn
        pin on the SK1 connector is an output!)
      1.  Internal 10 MHz clock.
      2.  Internal 1 MHz clock.
      3.  Internal 100 kHz clock.
      4.  Internal 10 kHz clock.
      5.  Internal 1 kHz clock.
      6.  OUT n-1, the output of counter channel n-1 (see note 1 below).
      7.  Ext Clock, the counter chip's dedicated Ext Clock input from
        the SK1 connector.  This pin is shared by all three counter
        channels on the chip.

  INSN_CONFIG_GET_CLOCK_SRC.  Returns the counter channel's current
    clock source in data[1].  For internal clock sources, data[2] is set
    to the period in ns.

  INSN_CONFIG_SET_GATE_SRC.  Sets the counter channel's gate source as
    specified in data[2] (this is a hardware-specific value).  Not
    supported on PC214E.  For the other boards, valid gate sources are 0
    to 7 as follows:

      0.  VCC (internal +5V d.c.), i.e. gate permanently enabled.
      1.  GND (internal 0V d.c.), i.e. gate permanently disabled.
      2.  GAT n, the counter channel's dedicated GAT input from the SK1
        connector.  (N.B. for other values, the counter channel's GATn
        pin on the SK1 connector is an output!)
      3.  /OUT n-2, the inverted output of counter channel n-2 (see note
        2 below).
      4.  Reserved.
      5.  Reserved.
      6.  Reserved.
      7.  Reserved.

  INSN_CONFIG_GET_GATE_SRC.  Returns the counter channel's current gate
    source in data[2].

Clock and gate interconnection notes:

  1.  Clock source OUT n-1 is the output of the preceding channel on the
  same counter subdevice if n > 0, or the output of channel 2 on the
  preceding counter subdevice (see note 3) if n = 0.

  2.  Gate source /OUT n-2 is the inverted output of channel 0 on the
  same counter subdevice if n = 2, or the inverted output of channel n+1
  on the preceding counter subdevice (see note 3) if n < 2.

  3.  The counter subdevices are connected in a ring, so the highest
  counter subdevice precedes the lowest.

The 'TIMER' subdevice is a free-running 32-bit timer subdevice.

The 'INTERRUPT' subdevice pretends to be a digital input subdevice.  The
digital inputs come from the interrupt status register.  The number of
channels matches the number of interrupt sources.  The PC214E does not
have an interrupt status register; see notes on 'INTERRUPT SOURCES'
below.

INTERRUPT SOURCES

                    PC212E         PC214E      PC215E/PCI215
                 -------------  -------------  -------------
  Sources              6              1              6
   0               PPI-X-C0       JUMPER-J5      PPI-X-C0
   1               PPI-X-C3                      PPI-X-C3
   2              CTR-Y1-OUT1                    PPI-Y-C0
   3              CTR-Y2-OUT1                    PPI-Y-C3
   4              CTR-Z1-OUT1                   CTR-Z1-OUT1
   5              CTR-Z2-OUT1                   CTR-Z2-OUT1

                    PCIe215        PC218E         PCIe236
                 -------------  -------------  -------------
  Sources              6              6              6
   0               PPI-X-C0      CTR-X1-OUT1     PPI-X-C0
   1               PPI-X-C3      CTR-X2-OUT1     PPI-X-C3
   2               PPI-Y-C0      CTR-Y1-OUT1      unused
   3               PPI-Y-C3      CTR-Y2-OUT1      unused
   4              CTR-Z1-OUT1    CTR-Z1-OUT1    CTR-Z1-OUT1
   5              CTR-Z2-OUT1    CTR-Z2-OUT1    CTR-Z2-OUT1

                 PC272E/PCI272     PCIe296
                 -------------  -------------
  Sources              6              6
   0               PPI-X-C0       PPI-X1-C0
   1               PPI-X-C3       PPI-X1-C3
   2               PPI-Y-C0       PPI-Y1-C0
   3               PPI-Y-C3       PPI-Y1-C3
   4               PPI-Z-C0      CTR-Z1-OUT1
   5               PPI-Z-C3      CTR-Z2-OUT1

When an interrupt source is enabled in the interrupt source enable
register, a rising edge on the source signal latches the corresponding
bit to 1 in the interrupt status register.

When the interrupt status register value as a whole (actually, just the
6 least significant bits) goes from zero to non-zero, the board will
generate an interrupt.  For level-triggered hardware interrupts (PCI
card), the interrupt will remain asserted until the interrupt status
register is cleared to zero.  For edge-triggered hardware interrupts
(ISA card), no further interrupts will occur until the interrupt status
register is cleared to zero.  To clear a bit to zero in the interrupt
status register, the corresponding interrupt source must be disabled
in the interrupt source enable register (there is no separate interrupt
clear register).

The PC214E does not have an interrupt source enable register or an
interrupt status register; its 'INTERRUPT' subdevice has a single
channel and its interrupt source is selected by the position of jumper
J5.

COMMANDS

The driver supports a read streaming acquisition command on the
'INTERRUPT' subdevice.  The channel list selects the interrupt sources
to be enabled.  All channels will be sampled together (convert_src ==
TRIG_NOW).  The scan begins a short time after the hardware interrupt
occurs, subject to interrupt latencies (scan_begin_src == TRIG_EXT,
scan_begin_arg == 0).  The value read from the interrupt status register
is packed into a sampl_t value, one bit per requested channel, in the
order they appear in the channel list.




  

Author: Ian Abbott <abbotti@mev.co.uk>

Status: works

Configuration options - PC36AT:
  [0] - I/O port base address
  [1] - IRQ (optional)

Configuration options - PCI236:
  [0] - PCI bus of device (optional)
  [1] - PCI slot of device (optional)
  If bus/slot is not specified, the first available PCI device will be
  used.

The PC36AT ISA board and PCI236 PCI board have a single 8255 appearing
as subdevice 0.

Subdevice 1 pretends to be a digital input device, but it always returns
0 when read. However, if you run a command with scan_begin_src=TRIG_EXT,
a rising edge on port C bit 3 acts as an external trigger, which can be
used to wake up tasks.  This is like the comedi_parport device, but the
only way to physically disable the interrupt on the PC36AT is to remove
the IRQ jumper.  If no interrupt is connected, then subdevice 1 is
unused.




  

Author: Ian Abbott <abbotti@mev.co.uk>

Status: works

Configuration options - PC263:
  [0] - I/O port base address

Configuration options - PCI263:
  [0] - PCI bus of device (optional)
  [1] - PCI slot of device (optional)
  If bus/slot is not specified, the first available PCI device will be
  used.

Each board appears as one subdevice, with 16 digital outputs, each
connected to a reed-relay. Relay contacts are closed when output is 1.
The state of the outputs can be read.




  

Author: Ian Abbott <abbotti@mev.co.uk>

Status: works, but see caveats

  - ao_insn read/write
  - ao_do_cmd mode with the following sources:

    - start_src         TRIG_INT        TRIG_EXT
    - scan_begin_src    TRIG_TIMER      TRIG_EXT
    - convert_src       TRIG_NOW
    - scan_end_src      TRIG_COUNT
    - stop_src          TRIG_COUNT      TRIG_EXT        TRIG_NONE

    The channel list must contain at least one channel with no repeated
    channels.  The scan end count must equal the number of channels in
    the channel list.

    There is only one external trigger source so only one of start_src,
    scan_begin_src or stop_src may use TRIG_EXT.

Configuration options - PCI224:
  [0] - PCI bus of device (optional).
  [1] - PCI slot of device (optional).
          If bus/slot is not specified, the first available PCI device
          will be used.
  [2] - Select available ranges according to jumper LK1.  All channels
        are set to the same range:
        0=Jumper position 1-2 (factory default), 4 software-selectable
          internal voltage references, giving 4 bipolar and 4 unipolar
          ranges:
            [-10V,+10V], [-5V,+5V], [-2.5V,+2.5V], [-1.25V,+1.25V],
            [0,+10V], [0,+5V], [0,+2.5V], [0,1.25V].
        1=Jumper position 2-3, 1 external voltage reference, giving
          1 bipolar and 1 unipolar range:
            [-Vext,+Vext], [0,+Vext].

Configuration options - PCI234:
  [0] - PCI bus of device (optional).
  [1] - PCI slot of device (optional).
          If bus/slot is not specified, the first available PCI device
          will be used.
  [2] - Select internal or external voltage reference according to
        jumper LK1.  This affects all channels:
        0=Jumper position 1-2 (factory default), Vref=5V internal.
        1=Jumper position 2-3, Vref=Vext external.
  [3] - Select channel 0 range according to jumper LK2:
        0=Jumper position 2-3 (factory default), range [-2*Vref,+2*Vref]
          (10V bipolar when options[2]=0).
        1=Jumper position 1-2, range [-Vref,+Vref]
          (5V bipolar when options[2]=0).
  [4] - Select channel 1 range according to jumper LK3: cf. options[3].
  [5] - Select channel 2 range according to jumper LK4: cf. options[3].
  [6] - Select channel 3 range according to jumper LK5: cf. options[3].

Passing a zero for an option is the same as leaving it unspecified.


  1) All channels on the PCI224 share the same range.  Any change to the
     range as a result of insn_write or a streaming command will affect
     the output voltages of all channels, including those not specified
     by the instruction or command.

  2) For the analog output command,  the first scan may be triggered
     falsely at the start of acquisition.  This occurs when the DAC scan
     trigger source is switched from 'none' to 'timer' (scan_begin_src =
     TRIG_TIMER) or 'external' (scan_begin_src == TRIG_EXT) at the start
     of acquisition and the trigger source is at logic level 1 at the
     time of the switch.  This is very likely for TRIG_TIMER.  For
     TRIG_EXT, it depends on the state of the external line and whether
     the CR_INVERT flag has been set.  The remaining scans are triggered
     correctly.




  

Author: Allan Willcox <allanwillcox@ozemail.com.au>, Steve D Sharples <steve.sharples@nottingham.ac.uk>, Ian Abbott <abbotti@mev.co.uk>

Status: works

Configuration options:
  [0] - PCI bus of device (optional).
  [1] - PCI slot of device (optional).
          If bus/slot is not specified, the first available PCI device
          will be used.

Configuring a "amplc_pci230" will match any supported card and it will
choose the best match, picking the "+" models if possible.  Configuring
a "pci230" will match a PCI230 or PCI230+ card and it will be treated as
a PCI230.  Configuring a "pci260" will match a PCI260 or PCI260+ card
and it will be treated as a PCI260.  Configuring a "pci230+" will match
a PCI230+ card.  Configuring a "pci260+" will match a PCI260+ card.


                PCI230(+)    PCI260(+)
                ---------    ---------
  Subdevices       3            1
        0          AI           AI
	1          AO
	2          DIO

AI Subdevice:

  The AI subdevice has 16 single-ended channels or 8 differential
  channels.

  The PCI230 and PCI260 cards have 12-bit resolution.  The PCI230+ and
  PCI260+ cards have 16-bit resolution.

  For differential mode, use inputs 2N and 2N+1 for channel N (e.g. use
  inputs 14 and 15 for channel 7).  If the card is physically a PCI230
  or PCI260 then it actually uses a "pseudo-differential" mode where the
  inputs are sampled a few microseconds apart.  The PCI230+ and PCI260+
  use true differential sampling.  Another difference is that if the
  card is physically a PCI230 or PCI260, the inverting input is 2N,
  whereas for a PCI230+ or PCI260+ the inverting input is 2N+1.  So if a
  PCI230 is physically replaced by a PCI230+ (or a PCI260 with a
  PCI260+) and differential mode is used, the differential inputs need
  to be physically swapped on the connector.

  The following input ranges are supported:

    0 => [-10, +10] V
    1 => [-5, +5] V
    2 => [-2.5, +2.5] V
    3 => [-1.25, +1.25] V
    4 => [0, 10] V
    5 => [0, 5] V
    6 => [0, 2.5] V

AI Commands:

  +=========+==============+===========+============+==========+
  |start_src|scan_begin_src|convert_src|scan_end_src| stop_src |
  +=========+==============+===========+============+==========+
  |TRIG_NOW | TRIG_FOLLOW  |TRIG_TIMER | TRIG_COUNT |TRIG_NONE |
  |TRIG_INT |              |TRIG_EXT(3)|            |TRIG_COUNT|
  |         |              |TRIG_INT   |            |          |
  |         |--------------|-----------|            |          |
  |         | TRIG_TIMER(1)|TRIG_TIMER |            |          |
  |         | TRIG_EXT(2)  |           |            |          |
  |         | TRIG_INT     |           |            |          |
  +---------+--------------+-----------+------------+----------+

  Note 1: If AI command and AO command are used simultaneously, only
          one may have scan_begin_src == TRIG_TIMER.

  Note 2: For PCI230 and PCI230+, scan_begin_src == TRIG_EXT uses
          DIO channel 16 (pin 49) which will need to be configured as
          a digital input.  For PCI260+, the EXTTRIG/EXTCONVCLK input
          (pin 17) is used instead.  For PCI230, scan_begin_src ==
          TRIG_EXT is not supported.  The trigger is a rising edge
          on the input.

  Note 3: For convert_src == TRIG_EXT, the EXTTRIG/EXTCONVCLK input
          (pin 25 on PCI230(+), pin 17 on PCI260(+)) is used.  The
          convert_arg value is interpreted as follows:

            convert_arg == (CR_EDGE | 0) => rising edge
            convert_arg == (CR_EDGE | CR_INVERT | 0) => falling edge
            convert_arg == 0 => falling edge (backwards compatibility)
            convert_arg == 1 => rising edge (backwards compatibility)

  All entries in the channel list must use the same analogue reference.
  If the analogue reference is not AREF_DIFF (not differential) each
  pair of channel numbers (0 and 1, 2 and 3, etc.) must use the same
  input range.  The input ranges used in the sequence must be all
  bipolar (ranges 0 to 3) or all unipolar (ranges 4 to 6).  The channel
  sequence must consist of 1 or more identical subsequences.  Within the
  subsequence, channels must be in ascending order with no repeated
  channels.  For example, the following sequences are valid: 0 1 2 3
  (single valid subsequence), 0 2 3 5 0 2 3 5 (repeated valid
  subsequence), 1 1 1 1 (repeated valid subsequence).  The following
  sequences are invalid: 0 3 2 1 (invalid subsequence), 0 2 3 5 0 2 3
  (incompletely repeated subsequence).  Some versions of the PCI230+ and
  PCI260+ have a bug that requires a subsequence longer than one entry
  long to include channel 0.

AO Subdevice:

  The AO subdevice has 2 channels with 12-bit resolution.

  The following output ranges are supported:

    0 => [0, 10] V
    1 => [-10, +10] V

AO Commands:

  +=========+==============+===========+============+==========+
  |start_src|scan_begin_src|convert_src|scan_end_src| stop_src |
  +=========+==============+===========+============+==========+
  |TRIG_INT | TRIG_TIMER(1)| TRIG_NOW  | TRIG_COUNT |TRIG_NONE |
  |         | TRIG_EXT(2)  |           |            |TRIG_COUNT|
  |         | TRIG_INT     |           |            |          |
  +---------+--------------+-----------+------------+----------+

  Note 1: If AI command and AO command are used simultaneously, only
          one may have scan_begin_src == TRIG_TIMER.

  Note 2: scan_begin_src == TRIG_EXT is only supported if the card is
          configured as a PCI230+ and is only supported on later
          versions of the card.  As a card configured as a PCI230+ is
          not guaranteed to support external triggering, please consider
          this support to be a bonus.  It uses the EXTTRIG/ EXTCONVCLK
          input (PCI230+ pin 25).  Triggering will be on the rising edge
          unless the CR_INVERT flag is set in scan_begin_arg.

  The channels in the channel sequence must be in ascending order with
  no repeats.  All entries in the channel sequence must use the same
  output range.

DIO Subdevice:

  The DIO subdevice is a 8255 chip providing 24 DIO channels.  The DIO
  channels are configurable as inputs or outputs in four groups:

    Port A  - channels  0 to  7
    Port B  - channels  8 to 15
    Port CL - channels 16 to 19
    Port CH - channels 20 to 23

  Only mode 0 of the 8255 chip is supported.

  Bit 0 of port C (DIO channel 16) is also used as an external scan
  trigger input for AI commands on PCI230 and PCI230+, so would need to
  be configured as an input to use it for that purpose.




  

Author: Dan Block

Status: unknown

This driver will not work with a 2.4 kernel.




  

Author: ds

Status: experimental

Author: Oliver Gause

Status: works

Written to support the PCI-DAC6702. Trivially extended to support
the PCI-DAC6703, it has just 16 ao channels instead of 8.

Configuration Options:
    [0] - PCI bus number
    [1] - PCI slot number

Developed from cb_pcidas64, cb_pcimdas and skel. The register values are
taken from the register map of Measurement Computing.

Supports DIO, AO in its present form.




  

Author: Ivan Martinez <imr@oersted.dtu.dk>, Frank Mori Hess <fmhess@users.sourceforge.net>, Brice Dubost <braice@braice.net>

Status: There are many reports of the driver being used with most of the supported cards. Despite no detailed log is maintained, it can be said that the driver is quite tested and stable.

  The boards may be autocalibrated using the comedi_calibrate
  utility.

Configuration options:
  [0] - PCI bus of device (optional)
  [1] - PCI slot of device (optional)
  If bus/slot is not specified, the first supported
  PCI device found will be used.

For commands, the scanned channels must be consecutive
(i.e. 4-5-6-7, 2-3-4,...), and must all have the same
range and aref.

AI Triggering:
   For start_src == TRIG_EXT, the A/D EXTERNAL TRIGGER IN (pin 45) is used.
   For 1602 series, the start_arg is interpreted as follows:
     start_arg == 0                   => gated triger (level high)
     start_arg == CR_INVERT           => gated triger (level low)
     start_arg == CR_EDGE             => Rising edge
     start_arg == CR_EDGE | CR_INVERT => Falling edge
   For the other boards the trigger will be done on rising edge




  

Author: Frank Mori Hess <fmhess@users.sourceforge.net>

Status: works

Configuration options:
   [0] - PCI bus of device (optional)
   [1] - PCI slot of device (optional)

These boards may be autocalibrated with the comedi_calibrate utility.

To select the bnc trigger input on the 4020 (instead of the dio input),
specify a nonzero channel in the chanspec.  If you wish to use an external
master clock on the 4020, you may do so by setting the scan_begin_src
to TRIG_OTHER, and using an INSN_CONFIG_TIMER_1 configuration insn
to configure the divisor to use for the external clock.

Some devices are not identified because the PCI device IDs are not yet
known. If you have such a board, please file a bug report at




  

Author: Ivan Martinez <ivanmr@altavista.com>, Frank Mori Hess <fmhess@users.sourceforge.net>

Status: Supports 08/16, 04/16, 02/16, 08/12, 04/12, and 02/12

Configuration options:
  [0] - PCI bus of device (optional)
  [1] - PCI slot of device (optional)
  If bus/slot is not specified, the first available PCI
  device will be used.

Only simple analog output writing is supported.

So far it has only been tested with:
  - PCI-DDA08/12
Please report success/failure with other different cards to
<comedi@comedi.org>.




  

Author: Yoshiya Matsuzaka

Status: experimental

This driver has been modified from skel.c of comedi-0.7.70.

Configuration Options:
  [0] - PCI bus of device (optional)
  [1] - PCI slot of device (optional)
  If bus/slot is not specified, the first available PCI device will
  be used.

Passing a zero for an option is the same as leaving it unspecified.




  

Author: Richard Bytheway

Status: experimental

Written to support the PCIM-DAS1602/16 and PCIe-DAS1602/16.

Configuration Options:
    [0] - PCI bus number
    [1] - PCI slot number

Developed from cb_pcidas and skel by Richard Bytheway (mocelet@sucs.org).
Only supports DIO, AO and simple AI in it's present form.
No interrupts, multi channel or FIFO AI, although the card looks like it could
support this.





  

Author: Calin Culianu <calin@ajvar.org>

Status: works

All features of the PCIM-DDA06-16 board are supported.  This board
has 6 16-bit AO channels, and the usual 8255 DIO setup.  (24 channels,
configurable in banks of 8 and 4, etc.).  This board does not support commands.

The board has a peculiar way of specifying AO gain/range settings -- You have
1 jumper bank on the card, which either makes all 6 AO channels either
5 Volt unipolar, 5V bipolar, 10 Volt unipolar or 10V bipolar.

Since there is absolutely _no_ way to tell in software how this jumper is set
(well, at least according  to the rather thin spec. from Measurement Computing
 that comes with the board), the driver assumes the jumper is at its factory
default setting of +/-5V.

Also of note is the fact that this board features another jumper, whose
state is also completely invisible to software.  It toggles two possible AO
output modes on the board:

  - Update Mode: Writing to an AO channel instantaneously updates the actual
    signal output by the DAC on the board (this is the factory default).
  - Simultaneous XFER Mode: Writing to an AO channel has no effect until
    you read from any one of the AO channels.  This is useful for loading
    all 6 AO values, and then reading from any one of the AO channels on the
    device to instantly update all 6 AO values in unison.  Useful for some
    control apps, I would assume?  If your jumper is in this setting, then you
    need to issue your comedi_data_write()s to load all the values you want,
    then issue one comedi_data_read() on any channel on the AO subdevice
    to initiate the simultaneous XFER.

Configuration Options:
  [0] PCI bus (optional)
  [1] PCI slot (optional)
  [2] analog output range jumper setting
      0 == +/- 5 V
      1 == +/- 10 V




  

Author: ds

Status: works

This driver allows you to 'bond' (merge) multiple comedi subdevices
(coming from possibly difference boards and/or drivers) together.  For
example, if you had a board with 2 different DIO subdevices, and
another with 1 DIO subdevice, you could 'bond' them with this driver
so that they look like one big fat DIO subdevice.  This makes writing
applications slightly easier as you don't have to worry about managing
different subdevices in the application -- you just worry about
indexing one linear array of channel id's.

Right now only DIO subdevices are supported as that's the personal itch
I am scratching with this driver.  If you want to add support for AI and AO
subdevs, go right on ahead and do so!

Commands aren't supported -- although it would be cool if they were.

Configuration Options:
  List of comedi-minors to bond.  All subdevices of the same type
  within each minor will be concatenated together in the order given here.




  

Author: ds

Status: works in immediate mode

A cheap and easy way to get a few more digital I/O lines.  Steal
additional parallel ports from old computers or your neighbors'
computers.

Option list:
 0: I/O port base for the parallel port.
 1: IRQ

Parallel Port Lines:

pin     subdev  chan    aka
---     ------  ----    ---
1       2       0       strobe
2       0       0       data 0
3       0       1       data 1
4       0       2       data 2
5       0       3       data 3
6       0       4       data 4
7       0       5       data 5
8       0       6       data 6
9       0       7       data 7
10      1       3       acknowledge
11      1       4       busy
12      1       2       output
13      1       1       printer selected
14      2       1       auto LF
15      1       0       error
16      2       2       init
17      2       3       select printer
18-25   ground


Subdevices 0 is digital I/O, subdevice 1 is digital input, and
subdevice 2 is digital output.  Unlike other Comedi devices,
subdevice 0 defaults to output.

Pins 13 and 14 are inverted once by Comedi and once by the
hardware, thus cancelling the effect.

Pin 1 is a strobe, thus acts like one.  There's no way in software
to change this, at least on a standard parallel port.

Subdevice 3 pretends to be a digital input subdevice, but it always
returns 0 when read.  However, if you run a command with
scan_begin_src=TRIG_EXT, it uses pin 10 as a external triggering
pin, which can be used to wake up tasks.




  

Author: ds, fmhess

Status: works

This driver requires RTAI or RTLinux to work correctly.  It doesn't
actually drive hardware directly, but calls other drivers and uses
a real-time task to emulate commands for drivers and devices that
are incapable of native commands.  Thus, you can get accurately
timed I/O on any device.

Since the timing is all done in software, sampling jitter is much
higher than with a device that has an on-board timer, and maximum
sample rate is much lower.

Configuration options:
  [0] - minor number of device you wish to emulate commands for
  [1] - subdevice number you wish to emulate commands for




  

Author: Joachim Wuttke <Joachim.Wuttke@icn.siemens.de>, Frank Mori Hess <fmhess@users.sourceforge.net>, ds

Status: works

This driver is mainly for testing purposes, but can also be used to
generate sample waveforms on systems that don't have data acquisition
hardware.

Configuration options:
  [0] - Amplitude in microvolts for fake waveforms (default 1 volt)
  [1] - Period in microseconds for fake waveforms (default 0.1 sec)

Generates a sawtooth wave on channel 0, square wave on channel 1, additional
waveforms could be added to other channels (currently they return flatline
zero volts).




  

Author: Contec Co., Ltd.

Status: works

Configuration Options:
  [0] - DeviceID of module (optional)
  If DeviceID is not specified, DeviceID 0 will be used.




  

Author: Stefano Rivoir <s.rivoir@gts.it>

Status: works

Configuration Options:
  [0] - PCI bus of device (optional)
  [1] - PCI slot of device (optional)
  If bus/slot is not specified, the first supported
  PCI device found will be used.




  

Author: Anders Blomdell <anders.blomdell@control.lth.se>

Status: works

Much of the functionality of this driver was determined from reading
the source code for the Windows driver.

The FPGA on the board requires initialization code, which can
be loaded by comedi_config using the -i
option.  The initialization code is available from http://www.comedi.org
in the comedi_nonfree_firmware tarball.

Configuration options:
  [0] - PCI bus of device (optional)
  [1] - PCI slot of device (optional)
  If bus/slot is not specified, the first supported
  PCI device found will be used.




  

Author: Warren Jasper, ds, Frank Hess

Status: works

This is a rewrite of the das08 and das08jr drivers.

Options (for ISA cards):
        [0] - base io address

Options (for pci-das08):
        [0] - bus  (optional)
        [1] = slot (optional)

The das08 driver doesn't support asynchronous commands, since
the cheap das08 hardware doesn't really support them.  The
comedi_rt_timer driver can be used to emulate commands for this
driver.




  

Author: Warren Jasper, ds, Frank Hess

Status: works

This is the PCMCIA-specific support split off from the
das08 driver.

Options (for pcm-das08):
        NONE

Command support does not exist, but could be added for this board.




  

Author: Sam Moore, Warren Jasper, ds, Chris Baugher, Frank Hess, Roman Fietze

Status: works

A rewrite of the das16 and das1600 drivers.

Passing a zero for an option is the same as leaving it unspecified.




  

Author: Frank Mori Hess <fmhess@users.sourceforge.net>

Status: works

This driver supports a single board - the CIO-DAS16/M1.
As far as I know, there are no other boards that have
the same register layout.  Even the CIO-DAS16/M1/16 is
significantly different.

I was _barely_ able to reach the full 1 MHz capability
of this board, using a hard real-time interrupt
(set the TRIG_RT flag in your comedi_cmd and use
rtlinux or RTAI).  The board can't do dma, so the bottleneck is
pulling the data across the ISA bus.  I timed the interrupt
handler, and it took my computer ~470 microseconds to pull 512
samples from the board.  So at 1 Mhz sampling rate,
expect your CPU to be spending almost all of its
time in the interrupt handler.

This board has some unusual restrictions for its channel/gain list.  If the
list has 2 or more channels in it, then two conditions must be satisfied:
(1) - even/odd channels must appear at even/odd indices in the list
(2) - the list must have an even number of entries.


irq can be omitted, although the cmd interface will not work without it.




  

Author: Frank Mori Hess <fmhess@users.sourceforge.net>

Status: works

The waveform analog output on the 'ao' cards is not supported.
If you need it, send me (Frank Hess) an email.

Configuration options:
  [0] - I/O port base address
  [1] - IRQ (optional, required for timed or externally triggered conversions)
  [2] - DMA0 (optional, requires irq)
  [3] - DMA1 (optional, requires irq and dma0)




  

Author: Oystein Svendsen <svendsen@pvv.org>

Status: bitrotten

This driver has suffered bitrot.




  

Author: Frank Mori Hess <fmhess@users.sourceforge.net>

Status: works, cio-das802/16 untested - email me if you have tested it

Configuration options:
  [0] - I/O port base address
  [1] - IRQ (optional, required for timed or externally triggered conversions)


	All entries in the channel/gain list must use the same gain and be
	consecutive channels counting upwards in channel number (these are
	hardware limitations.)

	I've never tested the gain setting stuff since I only have a
	DAS-800 board with fixed gain.

	The cio-das802/16 does not have a fifo-empty status bit!  Therefore
	only fifo-half-full transfers are possible with this card.




  

Author: Perry J. Piplani <perry.j.piplani@nasa.gov>

Status: experimental

This driver is for the Diamond Systems MM-32-AT board

Configuration Options:
  [0] - I/O port base address
  [1] - IRQ (optional, required for timed conversions)
  [2] - Autocalibration control for MM-32X-AT and MM-32DX-AT
        0 - no change
	1 - disable autocalibration (ACHOLD)
	2 - enable temperature-triggered autocalibration (ACREL)




  

Author: ds

Status: works

This driver can autoprobe the type of board.

Configuration options:
  [0] - I/O port base address
  [1] - unused
  [2] - A/D reference 0=differential, 1=single-ended
  [3] - A/D range
          0 = [-10,10]
	  1 = [0,10]
  [4] - D/A 0 range
          0 = [-10,10]
	  1 = [-5,5]
	  2 = [-2.5,2.5]
	  3 = [0,10]
	  4 = [0,5]
  [5] - D/A 1 range (same choices)




  

Author: ds

Status: works

Configuration options:
  [0] - I/O port base address
  [1] - IRQ, although this is currently unused
  [2] - A/D reference
          0 = single-ended
          1 = differential
	  2 = pseudo-differential (common reference)
  [3] - A/D range
          0 = [-5,5]
	  1 = [-2.5,2.5]
	  2 = [0,5]
  [4] - D/A 0 range (same choices)
  [4] - D/A 1 range (same choices)




  

Author: ds

Status: complete

Configuration options:
  [0] - I/O port base address
  [1] - IRQ

This card has 16 analog inputs multiplexed onto a 12 bit ADC.  There
is a minimally useful onboard clock.  The base frequency for the
clock is selected by jumpers, and the clock divider can be selected
via programmed I/O.  Unfortunately, the clock divider can only be
a power of 10, from 1 to 10^7, of which only 3 or 4 are useful.  In
addition, the clock does not seem to be very accurate.




  

Author: ds

Status: mostly complete, untested

I'm not sure anyone has ever tested this board.  If you have information
contrary, please update.

Configuration options:
  [0] - I/O port base base address
  [1] - IRQ (unused)
  [2] - Voltage unipolar/bipolar configuration
          0 == unipolar 5V  (0V -- +5V)
	  1 == bipolar 5V  (-5V -- +5V)
  [3] - Current offset configuration
          0 == disabled  (0mA -- +32mAV)
          1 == enabled  (+4mA -- +20mAV)
  [4] - Firmware program configuration
          0 == program 1 (see manual table 5-4)
          1 == program 2 (see manual table 5-4)
          2 == program 3 (see manual table 5-4)
          3 == program 4 (see manual table 5-4)
  [5] - Analog output 0 range configuration
          0 == voltage
          1 == current
  [6] - Analog output 1 range configuration (same options)
  [7] - Analog output 2 range configuration (same options)
  [8] - Analog output 3 range configuration (same options)
  [9] - Analog output 4 range configuration (same options)
  [10] - Analog output 5 range configuration (same options)
  [11] - Analog output 6 range configuration (same options)
  [12] - Analog output 7 range configuration (same options)




  

Author: ds

Status: complete

A very simple digital I/O card.  Four banks of 8 lines, each bank
is configurable for input or output.  One wonders why it takes a
50 page manual to describe this thing.

The driver (which, btw, is much less than 50 pages) has 1 subdevice
with 32 channels, configurable in groups of 8.

Configuration options:
  [0] - I/O port base base address




  

Author: ds

Status: complete

Configuration options:
  [0] - I/O port base address
  [1] - IRQ
  [2] - DMA 1
  [3] - DMA 2
  [4] - AI jumpered for 0=single ended, 1=differential
  [5] - AI jumpered for 0=straight binary, 1=2's complement
  [6] - AO 0 jumpered for 0=straight binary, 1=2's complement
  [7] - AO 1 jumpered for 0=straight binary, 1=2's complement
  [8] - AI jumpered for 0=[-10,10]V, 1=[0,10], 2=[-5,5], 3=[0,5]
  [9] - AO 0 jumpered for 0=[-10,10]V, 1=[0,10], 2=[-5,5], 3=[0,5],
        4=[-2.5,2.5]
  [10]- A0 1 jumpered for 0=[-10,10]V, 1=[0,10], 2=[-5,5], 3=[0,5],
        4=[-2.5,2.5]





  

Author: ds

Status: works

Configuration Options:
  [0] - PCI bus of device (optional)
  [1] - PCI slot of device (optional)
  If bus/slot is not specified, the first supported
  PCI device found will be used.

There is code to support AI commands, but it may not work.

AO commands are not supported.




  

Author: anders.blomdell@control.lth.se (Anders Blomdell)

Status: in development

This driver works, but bulk transfers not implemented. Might be a starting point
for someone else. I found out too late that USB has too high latencies (>1 ms)
for my needs.




  

Author: Anders Gnistrup <ex18@kalman.iau.dtu.dk>

Status: unknown

Digital I/O is not supported.

Configuration options:
  [0] - I/O port base address




  

Author: Frank Mori Hess <fmhess@users.sourceforge.net>

Status: only receive mode works, transmit not supported

Configuration options:
   [0] - PCI bus of device (optional)
   [1] - PCI slot of device (optional)

There are some additional hpdi models available from GSC for which
support could be added to this driver.




  

Author: Anne Smorthit <anne.smorthit@sfwte.ch>

Status: works

The driver works for analog input and output and digital input and output.
It does not work with interrupts or with the counters.  Currently no support
for DMA.

It has 16 single-ended or 8 differential Analogue Input channels with 12-bit
resolution.  Ranges : 5V, 10V, +/-5V, +/-10V, 0..20mA and 4..20mA.  Input
ranges can be individually programmed for each channel.  Voltage or current
measurement is selected by jumper.

There are 4 x 12-bit Analogue Outputs.  Ranges : 5V, 10V, +/-5V, +/-10V

16 x Digital Inputs, 24V

8 x Digital Outputs, 24V, 1A

4 x 16-bit counters





  

Author: Markus Kempf <kempf@matsci.uni-sb.de>

Status: works

Supports the PCI-20001 C-2a Carrier board, and could probably support
the other carrier boards with small modifications.  Modules supported


options for PCI-20006M:
  first:   Analog output channel 0 range configuration
             0  bipolar 10  (-10V -- +10V)
             1  unipolar 10  (0V -- +10V)
             2  bipolar 5  (-5V -- 5V)
  second:  Analog output channel 1 range configuration

options for PCI-20341M:
  first:   Analog input gain configuration
             0  1
             1  10
             2  100
             3  200




  

Author: Anders Blomdell <anders.blomdell@control.lth.se>

Status: works

  The DSP on the board requires initialization code, which can
  be loaded by placing it in /lib/firmware/comedi.
  The initialization code should be somewhere on the media you got
  with your card. One version is available from http://www.comedi.org
  in the comedi_nonfree_firmware tarball.

  Configuration options:
  [0] - PCI bus number - if bus number and slot number are 0,
                         then driver search for first unused card
  [1] - PCI slot number




  

Author: Michael Hillmann

Status: tested

Configuration Options:
  [0] - PCI bus of device (optional)
  [1] - PCI slot of device (optional)
  If bus/slot is not specified, the first supported
  PCI device found will be used.

This driver is a simple driver to read the counter values from
Kolter Electronic PCI Counter Card.




  

Author: gg (Guenter Gebhardt <g.gebhardt@meilhaus.com>)

Status: broken (no support for loading firmware)

    - Analog Input
    - Analog Output
    - Digital I/O
    - Counter

Configuration Options:

    [0] - PCI bus number (optional)
    [1] - PCI slot number (optional)

    If bus/slot is not specified, the first available PCI
    device will be used.

The firmware required by these boards is available in the
comedi_nonfree_firmware tarball available from




  

Author: Michael Hillmann <hillmann@syscongroup.de>

Status: experimental

    Analog Output

Configuration options:

    [0] - PCI bus number (optional)
    [1] - PCI slot number (optional)

    If bus/slot is not specified, the first available PCI
    device will be used.

The 2600 requires a firmware upload, which can be accomplished
using the -i or --init-data option of comedi_config.
The firmware can be
found in the comedi_nonfree_firmware tarball available
from http://www.comedi.org




  

Author: Stanislaw Raczynski <sraczynski@op.pl>

Status: working

    The Micro/sys MPC-624 board is based on the LTC2440 24-bit sigma-delta
    ADC chip.
    
    Subdevices supported by the driver:
    - Analog In:   supported
    - Digital I/O: not supported
    - LEDs:        not supported
    - EEPROM:      not supported

Configuration Options:
  [0] - I/O base address
  [1] - convertion rate
            Convertion rate  RMS noise  Effective Number Of Bits
         0      3.52kHz        23uV                17
         1      1.76kHz       3.5uV                20
         2       880Hz         2uV                21.3
         3       440Hz        1.4uV               21.8
         4       220Hz         1uV                22.4
         5       110Hz        750uV               22.9
         6       55Hz         510nV               23.4
         7      27.5Hz        375nV                24 
         8      13.75Hz       250nV               24.4
         9      6.875Hz       200nV               24.6
   [2] - voltage range
         0      -1.01V .. +1.01V
         1      -10.1V .. +10.1V




  

Author: ds

Status: experimental

This driver is specific to the Motorola MPC8260 processor, allowing
you to access the processor's generic digital I/O lines.

It is apparently missing some code.




  

Author: Anders Blomdell <anders.blomdell@control.lth.se>

Status: works

Author: ds

Status: works

Author: Jon Grierson <jd@renko.co.uk>, Frank Mori Hess <fmhess@users.sourceforge.net>

Status: testing

Based on the PCI-6527 driver by ds.
The interrupt subdevice (subdevice 3) is probably broken for all boards
except maybe the 6514.




  

Author: J.P. Mellor <jpmellor@rose-hulman.edu>, Herman.Bruyninckx@mech.kuleuven.ac.be, Wim.Meeussen@mech.kuleuven.ac.be, Klaas.Gadeyne@mech.kuleuven.ac.be, Frank Mori Hess <fmhess@users.sourceforge.net>

Status: experimental

Encoders work.  PulseGeneration (both single pulse and pulse train)
works. Buffered commands work for input but not output.





  

Author: Bart Joris <bjoris@advalvas.be>

Status: unknown

Commands are not supported.




  

Author: Frank Mori Hess

Status: works

If you want to ac couple the board's inputs, use AREF_OTHER.

Configuration options:
  [0] - I/O port base address
  [1] - IRQ (optional, required for timed conversions)
  [2] - DMA (optional, required for timed conversions)




  

Author: ds

Status: should work

Configuration options:
  [0] - I/O port base address
  [1] - IRQ (unused)
  [2] - DMA (unused)
  [3] - analog output range, set by jumpers on hardware (0 for -10 to 10V bipolar, 1 for 0V to 10V unipolar)




  

Author: ds

Status: works

The driver has 2.6 kernel isapnp support, and
will automatically probe for a supported board if the
I/O base is left unspecified with comedi_config.
However, many of
the isapnp id numbers are unknown.  If your board is not
recognized, please send the output of 'cat /proc/isapnp'
(you may need to modprobe the isa-pnp module for
/proc/isapnp to exist) so the
id numbers for your board can be added to the driver.

Otherwise, you can use the isapnptools package to configure
your board.  Use isapnp to
configure the I/O base and IRQ for the board, and then pass
the same values as
parameters in comedi_config.  A sample isapnp.conf file is included
in the etc/ directory of Comedilib.

Comedilib includes a utility to autocalibrate these boards.  The
boards seem to boot into a state where the all calibration DACs
are at one extreme of their range, thus the default calibration
is terrible.  Calibration at boot is strongly encouraged.

To use the extended digital I/O on some of the boards, enable the
8255 driver when configuring the Comedi source tree.

External triggering is supported for some events.  The channel index
(scan_begin_arg, etc.) maps to PFI0 - PFI9.

Some of the more esoteric triggering possibilities of these boards
are not supported.




  

Author: Chris R. Baugher <baugher@enteract.com>

Status: unknown

Author: Fred Brooks <nsaspook@nsaspook.com>, based on ni_daq_dio24 by Daniel Vecino Castel <dvecino@able.es>

Status: works

The daqcard-700 appears in Comedi as a single digital I/O subdevice with
16 channels.  The channel 0 corresponds to the daqcard-700's output
port, bit 0; channel 8 corresponds to the input port, bit 0.

Direction configuration: channels 0-7 output, 8-15 input (8225 device
emu as port A output, port B input, port C N/A).

IRQ is assigned but not used.




  

Author: Daniel Vecino Castel <dvecino@able.es>

Status: ?

This is just a wrapper around the 8255.o driver to properly handle
the PCMCIA interface.




  

Author: Frank Mori Hess <fmhess@users.sourceforge.net>

Status: works

Tested with lab-pc-1200.  For the older Lab-PC+, not all input ranges
and analog references will work, the available ranges/arefs will
depend on how you have configured the jumpers on your board
(see your owner's manual).

Kernel-level ISA plug-and-play support for the lab-pc-1200
boards has not
yet been added to the driver, mainly due to the fact that
I don't know the device id numbers.  If you have one
of these boards,
please file a bug report at https://bugs.comedi.org/
so I can get the necessary information from you.

The 1200 series boards have onboard calibration dacs for correcting
analog input/output offsets and gains.  The proper settings for these
caldacs are stored on the board's eeprom.  To read the caldac values
from the eeprom and store them into a file that can be then be used by
comedilib, use the comedi_calibrate program.

Configuration options - ISA boards:
  [0] - I/O port base address
  [1] - IRQ (optional, required for timed or externally triggered conversions)
  [2] - DMA channel (optional)

Configuration options - PCI boards:
  [0] - bus (optional)
  [1] - slot (optional)

The Lab-pc+ has quirky chanlist requirements
when scanning multiple channels.  Multiple channel scan
sequence must start at highest channel, then decrement down to
channel 0.  The rest of the cards can scan down like lab-pc+ or scan
up from channel zero.  Chanlists consisting of all one channel
are also legal, and allow you to pace conversions in bursts.




  

Author: Frank Mori Hess <fmhess@users.sourceforge.net>

Status: works

Thanks go to Fredrik Lingvall for much testing and perseverance in
helping to debug daqcard-1200 support.

The 1200 series boards have onboard calibration dacs for correcting
analog input/output offsets and gains.  The proper settings for these
caldacs are stored on the board's eeprom.  To read the caldac values
from the eeprom and store them into a file that can be then be used by
comedilib, use the comedi_calibrate program.

Configuration options:
  none

The daqcard-1200 has quirky chanlist requirements
when scanning multiple channels.  Multiple channel scan
sequence must start at highest channel, then decrement down to
channel 0.  Chanlists consisting of all one channel
are also legal, and allow you to pace conversions in bursts.




  

Author: ds

Status: works

See the notes in the ni_atmio.o driver.




  

Author: ds

Status: works

The DIO-96 appears as four 8255 subdevices.  See the 8255
driver notes for details.

The DIO32HS board appears as one subdevice, with 32 channels.
Each channel is individually I/O configurable.  The channel order
is 0=A0, 1=A1, 2=A2, ... 8=B0, 16=C0, 24=D0.  The driver only
supports simple digital I/O; no handshaking is supported.

DMA mostly works for the PCI-DIO32HS, but only in timed input mode.

The PCI-DIO-32HS/PCI-6533 has a configurable external trigger. Setting
scan_begin_arg to 0 or CR_EDGE triggers on the leading edge. Setting
scan_begin_arg to CR_INVERT or (CR_EDGE | CR_INVERT) triggers on the
trailing edge.

This driver could be easily modified to support AT-MIO32HS and
AT-MIO96.

The PCI-6534 requires a firmware upload after power-up to work, the
firmware data and instructions for loading it with comedi_config
it are contained in the
comedi_nonfree_firmware tarball available from http://www.comedi.org




  

Author: ds, John Hallen, Frank Mori Hess, Rolf Mueller, Herbert Peremans, Herman Bruyninckx, Terry Barnaby

Status: works